外文翻译三星S3C2442B 32位精简指令应用处理器用户手册.docx

1、外文翻译三星S3C2442B 32位精简指令应用处理器用户手册英文资料S3C2442B 32-BIT RISC APPLICATION PROCESSORUSERS MANUALINTRODUCTION This users manual describes SAMSUNGs SC32442B 16/32-bit RISC microprocessor. SAMSUNGs SC32442B is designed to provide hand-held devices and general applications with low-power, and high-performance

2、micro-controller solution in small die size. To reduce total system cost, the SC32442B includes the following components. The SC32442B is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for

3、 cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The SC32442B offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AM

4、BA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the SC32442B minimizes overall system costs and eliminates the need to configure additional components. The integrate

5、d on-chip functions that are described in this document include: Around 400MHz1.5V arm and 1.5V internal, 300MHz1.35V arm and 1.35V internal, 1.8Vmemory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU External memory controller (SDRAM Control and Chip Select logic) LCD controlle

6、r (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA 4-ch DMA controllers with external request pins 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) 2-ch SPls IIC bus interface (multi-master support) IIS Audio CODEC interface SD Host interface version 1.0 & MMC Protocol versio

7、n 2.11 compatible 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1) 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer 8-ch 10-bit ADC and Touch screen interface RTC with calendar function Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for

8、 scaling) 130 General Purpose I/O ports / 24-ch external interrupt source Power control: Normal, Slow, Idle, stop and Sleep mode On-chip clock generator with PLL FEATURES Architecture Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful

9、instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports the ARM debug archite

10、cture. Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB). System Manager Little/Big Endian support. Support Fast bus mode and Asynchronous bus mode. Address space: 128M bytes for each bank (total 1G bytes). Supports programmable 8/16/32-bit data bus width for each bank. Fi

11、xed bank start address from bank 0 to bank 6. Programmable bank start address and bank size for bank 7. Eight memory banks: Six memory banks for ROM, SRAM, Two memory banks for ROM/SRAM/ Synchronous DRAM. Complete Programmable access cycles for all memory banks. Supports external wait signals to exp

12、and the bus cycle. Supports self-refresh mode in SDRAM for power-down. Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others). NAND Flash Boot Loader Supports booting from NAND flash memory. 4KB internal buffer for booting. Supports storage memory for NAND flash memory after

13、booting. Supports Advanced NAND flash Cache Memory 64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB). 8words length per line with one valid bit and two dirty bits per line. Pseudo random or round robin replacement algorithm. Write-through or write-back cache operation to update the

14、 main memory. The write buffer can hold 16 words of data and four addresses. Clock & Power Manager On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 400MHz1.5V arm and 1.5V internal, 300MHz1.35V arm and 1.35V internal,. Clo

15、ck can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle, Deep-stop and Sleep mode Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Stop mode: All clocks are stopped. Deep-Stop mode: Arm po

16、wer off internal clocks are stopped. Sleep mode: The Core power including all peripherals is shut down. Woken up by EINT15:0 or RTC alarm interrupt from Sleep mode Stacked Memory 256Mbit or 512Mbit mSDR x32, VDD=1.8V 512Mbit or 1Gbit Nand Flash x8, VDD=1.8V Interrupt controller 59 Interrupt sources

17、(One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera) Level/Edge mode on external interrupt source Programmable polarity of edge and level Supports Fast Interrupt request (FIQ) for very urgent in

18、terrupt request Timer with Pulse Width Modulation (PWM) 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation Supports external clock sources RTC (Real Time Clock) Full clock feature:

19、msec, second, minute, hour, date, day, month, and year 32.768 KHz operation Alarm interrupt Time tick interrupt RTC Low Battery Check General Purpose Input/Output Ports 24 external interrupt ports 130 Multiplexed input/output ports DMA Controller 4-ch DMA controller Supports memory to memory, IO to

20、memory, memory to IO, and IO to IO transfers Burst transfer mode to enhance the transfer rate LCD Controller STN LCD Displays Feature Supports 3 types of STN LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type Supports monochrome mode, 4 gray levels, 16 gray levels, 256 co

21、lors and 4096 colors for STN LCD Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160, and others. Maximum frame buffer size is 4 Mbytes. Maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096 and others TFT(Thin Film Transistor) Color Displays

22、Feature Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT Supports 16, 24 bpp non-palette true-color displays for color TFT Supports maximum 16M color TFT at 24 bpp mode LPC3600 Timing controller embedded for LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait / 256K-color/ Reflective

23、a-Si TFT LCD) LCC3600 Timing controller embedded for LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait / 256K-color/ Transflective a-Si TFT LCD) Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160, and others. Maximum frame buffer size is 4Mbytes. Maximum virtual screen size in 64

24、K color mode : 2048x1024, and others UART 3-channel UART with DMA-based or interrupt-based operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx) Supports external clocks for the UART operation (UEXTCLK) Programmable baud rate Supports IrDA 1.0 Loopback mode for testin

25、g Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO. A/D Converter & Touch Screen Interface 8-ch multiplexed ADC Max. 500KSPS and 10-bit Resolution Internal FET for direct Touch screen interface Watchdog Timer 16-bit Watchdog Timer Interrupt request or system reset at time-out IIC-Bus In

26、terface 1-ch Multi-Master IIC-Bus Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode. IIS-Bus Interface 1-ch IIS-bus for audio interface with DMA-based operation Serial, 8-/16-bit per channel data transfers 128 B

27、ytes (64-Byte + 64-Byte) FIFO for Tx/Rx Supports IIS format and MSB-justified data format USB Host 2-port USB Host Complies with OHCI Rev. 1.0 Compatible with USB Specification version 1.1 USB Device 1-port USB Device 5 Endpoints for USB Device Compatible with USB Specification version 1.1 SD Host I

28、nterface Normal, Interrupt and DMA data transfer mode(byte, halfword, word transfer) DMA burst4 access support(only word transfer) Compatible with SD Memory Card Protocol version 1.0 Compatible with SDIO Card Protocol version 1.0 64 Bytes FIFO for Tx/Rx Compatible with Multimedia Card Protocol versi

29、on 2.11 SPI Interface Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11 2x8 bits Shift register for Tx/Rx DMA-based or interrupt-based operation Camera Interface ITU-R BT 601/656 8-bit mode support DZI (Digital Zoom In) capability Programmable polarity of video sync signals Max.

30、 4096 x 4096 pixels input support ( 2048 x 2048 pixel input support for scaling) Image mirror and rotation (X-axis mirror, Y-axis mirror, and 180 rotation) Camera output format (RGB 16/24-bit and YCbCr 4:2:0/4:2:2 format) Operating Voltage Range Core : 1.5V for 400MHz, 1.35V for 300MHz Internal : 1.5V for 400MHz and 1.35V for 300MHz Memory:1.8V for 100MHz or 133MHz I/O : 3.3V / 2.5V Operating Frequency Fclk Up to 400MHz or 300MHz Hclk Up to 133MHz or 100MHz Pclk Up to 66MHz or 50MHz Package 332-FBGA Block Diagram Pin Assignments译文三星S3C2442B 32位精简指令应用处理器用户手册绪言该用户手册描述了三星电子公司生产的SC32442B 16/32