51单片机外文文献.docx

1、51单片机外文文献The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performanee CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read on ly memory (PEROM). The device is manu faetured using Atmel lsigh-de nsity nonv olatile memory tech no logy and is compatible w

2、ith the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a mono lithic chip, the Atmel AT89C51 is a powerful microcomputer which prov

3、ides a highly-flexible and cost-effective solution to many embedded con trol applicati ons.Function characteristicThe AT89C51 provides the followi ng sta ndard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a ful

4、l duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero freque ncy and supports two software selectable power sav ing modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and in

5、terrupt system to continue fun cti oning. The Power-dow n Mode saves the RAM contents but freezes the oscillator disabli ng all other chip functions un til the n ext hardware reset.Pin DescriptionVCC Supply voltage.GND: Ground.Port 0Port 0 is an 8-bit ope n-dra in bi-directi onal I/O port. As an out

6、put port, each pin can si nk eight TTL in puts. When 1s are writte n to port 0 pins, the pin s can be used as high-impeda nce in puts. Port 0 may also be con figured to be the multiplexed address/data bus during accessesto external program and data memory. In this mode P0 has internal Pull-up resist

7、or. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during Program verification . External Pull-up resistors are required during Program verification .Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers

8、can sin k/source four TTL in puts. When 1s are writte n to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as in puts. As in puts, Port 1 pins that are exter nally being pulled low will source curre nt (IIL) because of the internal Pull-up resistors. Port 1 also re

9、ceives the low-order address bytes duri ng Flash program ming and verificati on.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 2 output buffers can sin k/source four TTL in puts. When 1s are writte n to Port 2 pins they are pulled high by the internal Pull-

10、up resistor and can be used as in puts. As in puts, Port 2 pins that are exter nally being pulled low will source curre nt, because of the internal Pull-up resistor. Port 2 emits the high-order address byte duri ng fetches from exter nal program memory and duri ng accesses to exter nal data memory t

11、hat use 16-bit addresses. In this application, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control

12、 signals during Flash programming and verificati on.Port 3Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3output buffers can sin k/source four TTL in puts. When 1s are writte n to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used a

13、s in puts. As in puts, Port 3 pins that are exter nally being pulled low will source curre nt (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port PinAUernate FunctionsP3.0RXD (serial input pert)P3.1TXD (serial output

14、 port)P3.2IMTO (external interrupt 0)P3.3INIT1 (external interrupt 1)P3,4TO (timer o external input)P3,5T1 (timer 1 external input)P3,6VVR (external data mennory write strobe)P3.7RD tKt&rnal data memory r&ad strobe)Port 3 also receives some control signals for Flash programming and verification.RSTR

15、eset in put. A high on this pin for two mach ine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address duri ng accesses to exter nal memory. This pin is also the program pulse in put (PROG) duri ng Flash program mi

16、n g. In no rmal operati on ALE is emitted at a con sta nt rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to exter nal Data Memory.If desired, ALE operation can be disabled by setting bit

17、0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC in structio n. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in exter nal executi on mode.PSENProgram Store En able is the read strobe to exter nal progra

18、m memory. Whe n the AT89C51 is executi ng code from exter nal program memory, PSENis activated twice each machi ne cycle, except that two PSEN activati ons are skipped duri ng each access to exter nal data memory.EA/VPPExternal Access En able. EA must be strapped to GND in order to en able the devic

19、e to fetchcode from exter nal program memory locati ons start ing at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be intern ally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltag

20、e (VPP) duri ng Flash program ming, for parts that require12-volt VPP.XTAL1In put to the inverting oscillator amplifier and in put to the internal clock operati ng circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the in put and output, respect

21、ively, of an inverting amplifier which can be con figured for use as an on-chip oscillator, as show n in Figure 1.Either a quartz crystal or ceramic reson ator may be used. To drive the device from an exter nal clock source, XTAL2 should be left unconn ected while XTAL1 is drive n asshow n in Figure

22、 2.There are no requireme nts on the duty cycle of the exter nal clock sig nal, since the in put to the internal clock ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.ftNDGNDCon figurati onIdle ModeIn idle mode, th

23、e CPU puts itself to sleep while all the on chip peripherals rema in active. The mode is inv oked by software. The content of the on-chip RAM and all the special fun cti ons registers rema in un cha nged duri ng this mode. The idle mode can be term in ated by any en abled in terrupt or by a hardware

24、 reset. It should be no ted that whe n idle is termi nated by a hard ware reset, the device no rmally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this eve nt, but ac

25、cess to the port pins is not in hibited. To elimi nate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to exter nal memory.Power-down ModeIn the power-dow n mode,

26、 the oscillator is stopped, and the in struct ion that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does

27、 not change the on-chip RAM. The reset should not be activated before VCC is restored to its no rmal operat ing level and must be held active long eno ugh to allow the oscillator to restart and stabilize.Status of External Pins Du和ng Idle and Power-down ModesModeALEPSENPORTOPORI1POAT2PORT3idiQ1 ntrn

28、al11DataDataDataDatahk?External11FleetDataAddressDataPzwer-dDwnInternal0DData缶饲alaDataPcwor downExiornsilD0冋aalDaiaDataDataProgram Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.L

29、ock B计 Protection ModesPragrair Lock P愣Prolvdlon TypsLB1LB2心1uUUNo proq-am lode tenures2PUuMOVC instruclions executedlfrom eKl&mai prcgrain memex ar& disabled from (etctiirtg cotk by値离 ion inlArrnl rm总irtory, rS 話 sarnplrd andilat:hAd on nd Fuither proqrmnnning .)f lh$ Flash dialed3PPuSame as m&do 2

30、. also vrly isAPPpSame as mode 3. alo external execut-on i：. dibbledWhe n lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a ran dom value, and holds that value un til reset is activated

31、. It is n ecessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.译文:AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS 8位单片机带有4K字节的可反复擦写 的程序存储器（PENROM。这种器件采用ATMEL公司的高密度、不容易丢失存 储技术生产，并且能够与 MCS-51系列的单片机兼容。片内含有8位中央处理器和闪烁存储单元，有较强的功能的 AT

32、89C51单片机能够被应用到控制领域中。功能特性AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据 存储器，32个I/O 口，2个16位定时/计数器，1个5向量两级中断结构，1个 串行通信口，片内震荡器和时钟电路。另外， AT89C51还可以进行OHZ的静态逻 辑操作，并支持两种软件的节电模式。闲散方式停止中央处理器的工作， 能够允 许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。掉电 方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件 的工作直到下一个复位。引脚描述VCC电源电压GND:地P0 口P0 口是一组8位漏极开路双向I/O 口，即地址/数据总线复用口。作为输出 口时，每一个管脚都能够驱动8个TTL电路。当“ 1被写入P0 口时，每个管脚都 能够作为高