计算机组成与体系结构B卷.docx

1、计算机组成与体系结构B卷姓名 学号 学院 专业 座位号 ( 密 封 线 内 不 答 题 )密封线线_ _ 诚信应考,考试作弊将带来严重后果！ 华南理工大学期末考试 计算机组成与体系结构 试卷B注意事项：1. 考前请将密封线内填写清楚； 2. 所有答案请直接答在试卷上； 3考试形式：闭卷； 4. 本试卷共 三 大题，满分100分， 考试时间120分钟。题 号一二三四五总分得 分评卷人I. 单项选择题（2 points each）Answer the question 1-2 based on the following information:A memory system uses 24-bi

2、t physical address. It has a direct-mapped cache with 64 entries. The block size is 4 words (word size is 4 bytes). Each cache entry has a “valid bit”, a “tag field”, and space for data.1. The number of bits reserved for the tag field is_.A. 14 B. 10 C. 6 D. 122. The total number of bits in the cach

3、e is_.A. 26*(143) B. 26*(33) C. 28*(145) D. 214*(33) 3. Which one of the following about one-address instruction is true? _A. One-address instruction has only one operandB. One-address instruction may have one operand or two operandsC. One-address instruction has two operands, and the other operand

4、is provided implicitlyD. One-address instruction may have three operands, and the other two operands are provided implicitly4. CPU responses the interrupt request_. A. after it completes its fetch cycleB. after it completes its execution cycleC. when the interrupt source issues the interrupt request

5、 D. when the bus is not busy5. The advantage of carry-lookahead adder is_. A. Optimize the structure of the adderB. Save hardware partsC. Accelerate the generation of the carriesD. Augment the structure of the adder6. In microprogram-controlled machines, the relationship between the machine instruct

6、ion and the microinstruction is_. A. a machine instruction is executed by a microinstructionB. a microinstruciton is composed of several machine instructionsC. a machine instruction is interpreted by a microroutine composed of microinstructionsD. a microroutine is executed by a machine instruction7.

7、 Once the DMA controller obtains access to the system bus, it transfers one byte of data and then returns the control of system to the processor. This DMA transfer mode is_. A. Burst Mode C. Cycle Stealing ModeB. Block Mode D. Transparent Mode8. Assume that the capacity of a kind of SRAM chip is 16K

8、32, so the sum of address lines and data lines of this chip is_. A. 48 B. 46 C. 36 D. 329. Assume that the multiplicand is 110011 and the multiplier is 101110. If multiply them using the Booth algorithm, then the Booth recoding multiplier is_. A. 1 1 0 0 1 0 C. 1 + 1 0 0 1 0 B. + 1 1 0 0 + 1 0 D. 1

9、+ 1 0 0 1 0 10. The microroutines for all instructions in the instruction set of a computer are stored in the .A. memory controller C. control store B. main memory D. cache11. _ is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. A. B

10、us protocol C. Bus timingB. Bus arbitration D. Bus transceiver12. _ has/have external fragmentation problem.A. Paging C. Segmentation with pagingB. Segmentation D. Segmentation and segmentation with paging13. The range and accuracy of floating-point numbers depend on_ respectively. A. The size of ex

11、ponent and the representation of mantissaB. The size of exponent and the size of mantissaC. The size of mantissa and the representation of exponentD. The size of mantissa and the size of exponent14. In a synchronous bus, controlling of data transfer on the bus is based on _. A. a common clock signal

12、 onlyB. a handshake signal onlyC. both clock signal and handshake signalD. either clock signal or handshake signal15. Which one of the following is not used to prevent data hazards? _A. BypassingB. ForwardingC. StallD. Freeze or FlushII. 简答题（5 points each）1. What is the difference between DRAM and S

13、RAM, in terms of characteristics such as speed, size, cost and application? Solution:2. In what circumstance will arithmetic overflow occur when two integers represented by 2s complement form are added? And write out the logic expression to detect overflow.Solution: 3. Describe the process of interr

14、upt processing. Solution:4. (5 points) What are the advantages and disadvantages of hardwired and microprogrammed control? Solution:III. 综合题（10 points each）1. Using nonrestoring division algorithm, perform the operations AB on the 5-bit unsigned numbers A= 10101 and B= 00101. Write the computation p

15、rocesses in a computer machine.Solution: 2. A byte-addressable computer has 16 address lines, 8 data lines, WR signal (read/write control signal) and MREQ signal (access memory control signal). Its address space includes:a) system program area ranging from 0 to 8191(decimal)b) user program area rang

16、ing from 8192 to 32767(decimal)c) and the last 2K address space for system program working areaThere are some memory chips: ROM: 8K8SRAM: 16K1, 2K8, 4K8, 8K8(1) Please specify how many chips to select to design the main memory of the computer.(2) Draw the logic structure figure of the main memory, a

17、nd the connection between the main memory and CPU.Solution:3. The following figure gives part of the microinstruction sequence corresponding to one of the machine instructions of a microprogrammed computer. Microinstruction B is followed by C, E, F, or I, depending on bits b6 and b5 of the machine i

18、nstruction register. Compare the two possible implementations described below. (1) Microinstruction sequencing is accomplished by means of a microprogram counter. Branching is achieved by microinstructions of the form: If b6b5 branch to X where b6b5 is the branch condition and X is the branch addres

19、s.(2) Same as (1) except that the branch microinstruction has the form:Branch to X, ORWhere X is a base branch address. The branch address is modified bybit-ORing of bits b5 and b6 with the appropriate bits with X.ABb6b5=11b6b5=10b6b5=00b6b5=01CEFIDGHJSolution:4. Consider a computer with 4M16 memory

20、 contains 97 instructions in its instruction set. The opcode length is fixed, and the addressing modes are direct, indirect, immediate, index, and relative. (Assume that the instruction length equals to word length) (1) Draw the figure of one-address instruction format, and specify the function of e

21、ach field.(2) Specify the max range of the direct addressing mode. (in decimal)(3) Specify the addressing range of one-level indirect addressing mode. (in decimal)(4) Specify the offset of the relative addressing mode. (in decimal)Solution: 5. A logic circuit is needed to implement the priority netw

22、ork shown like the following figure. The network handles three interrupt request lines. When a request is received on line INTRi, the network generates an acknowledgement on line INTAi. If more than one request is received, only the highest-priority request is acknowledged, where the ordering of priority is: priority of INTR1 priority of INTR2 priority of INTR3.(1) Give a truth table for each of the outputs INTA1, INTA2, and INTA3.(2) Give logic expressions of INTA1, INTA2, INTA3 and a logic circuit for implementing this priority network.Solution: