基于单片机的防盗报警器的设计英文翻译.docx

1、基于单片机的防盗报警器的设计英文翻译 本科生毕业设计（翻译）Multifunctional Intelligent Wireless Alarm SystemAbstract: Making use of rich inner resource of FPGA(Field Programmable Gate Arrays), a wireless alarm sending system is designed. It includes encoder, FSK(Frequency Shift Keying) modulation and every channels control circ

2、uits, which can decrease volume and increase reliability of the alarm system.The demodulation of receive system is realized by an application specific integrated circuits MC3372. With the help of a single-chip microcomputer 89C51, the address decoder is also designed in the receiver. Adding to other

3、 anti-interference,the alarming system has effectively decreased the error-alarm rate. The system can install up to 128 channel sending devices. It can send an alarm to the host when there are some cases in stand-off areas, and the system will display on rotation multiple cases area codes . The tran

4、smission distance is greater than 4Km in open zones. User can install more than one type sensors simultaneously, for example, smog sensor, combustible gas sensor or burglar sensor. Experiments show that the wireless alarm system has the strengths of high reliability, high anti-disturbance ability an

5、d low error-alarm rate. It can entirely meet the needs of alarm fireproofing and guard against theft, etc.Keywords: communication; Alarm systems; Frequency Shift Keying; Micro-controllers; Field Programmable Gate Arrays I.INTRODUCTION Compared with a wired alert system, a wireless alarm system has c

6、haracteristics of covertness and ease of installation. It is especially effective when transmitting between long distances in a complex landform situation. Made up of FPGA (Field Programmable Gate-Array), the encoding module in the sending system creates the address signal, FSK (frequency shift keyi

7、ng) modulates the signal and each channels controller signals. Using FPGA to replace MSI/SSI (Middle Scale Integrated or Small scale Integrated) digital circuit devices, not only increase the reliability and the resistance to interference of the alarm system, but it also decreases its volume and mak

8、es the system easier to install. Since used 7 bits binary number to express the address, up to 128 channels sender can be installed. The decoder consists of ASIC (Application Specific Integrated Circuit) and SCM in the wireless alarm receiver system, which can effectively decrease the error-alarm ra

9、te.II.THE SENDING SYSTEM PRINCIPLE Each stand-off is equipped with a wireless sending system,and corresponds with a 7 bits address identifier in binary. Once a case is detected by a sensor in any stand-off, a control signal of this area is sent to its encoding circuit via interface circuit, which co

10、nverts the areas 7bit address identifier into FSK signal. Then FSK signal is transmitted into a frequency modulation circuit for frequency modulating. After power amplification, the frequency modulation electromagnetic wave is emitted via antenna. One characteristic of the sending system is disconti

11、nuous sending. In other words, the sending system does not send signals when there is no case, and do keep sending when there is an alarm situation, so as to provide chances to send signals for other stand-off areas. A.The Encoding and Controlling Circuit Configuration The digital circuit part of th

12、e encoding circuit is made by a FPGA chip which includes 8 modules.Formed by D triggers, module dff1 is the interface between detector and encoder. Module oscillator combines with some external resistors and capacitors to form a controllable low frequency multivibrator. Its control signal is the out

13、put of dff1-Q1. It does not vibrate when Q1is equal to 0, and if Q1is equal to 1, it vibrates to generate low frequency square waves. If some cases appear in the area, the oscillator controls the module SENDER to send electromagnetic wave discontinuously. The module circular_shift_r is a parallel in

14、put serial output circular shift register. The bit A0A7 are the parallel address code input terminals, which are joined to high or low voltage level according to the encoder requirement. Q8 is the serial output terminal of the address code. Module dff2 is a control circuit that is made of some JK tr

15、iggers. Its setup signal is Q1, which also acts as a trigger signal after delay. Q2 acts as the parallel-in-serial-out control terminal of thecircular_shift_r module. When Q2 is at high voltage level,circular_shift_r performs parallel input. When Q2 is at low voltage level, circular_shift_r executes

16、 serial output. The module delay1 is a delay circuit composed of D triggers.The module division is a frequency division that creates three different routes frequency output signals, two of which branches and act as FSK modulating signals: f1 and f2. The other branch acts as a triggering pulse for mo

17、dules dff1 and delay1, and also acts as the clock pulse of circular_shift_rfor performing serial-out. The module MUX is a 2 to 1multiplexer. Its control signal is the output Q8 ofcircular_shift_r. When Q80, MUX produces the signal f2, and when Q81, it exports f1. The module delay2combines with some

18、external resistors and capacitors to form a delay circuit. Its function is to give workers some time to leave after installing the system. The sending circuit does no work within the delay time, no matter whether K1(detector) is on or off. This is the external connection drawing of the FPGA chip.B.

19、The Working Principle As shown following, the working principle of the alarm system is as follows: when the power of the sending system turns on, the input of the dff1 is at low level. Then its output terminal Q1 is at logic value 0, NQ1 is at logic 1, and a external light-emitting diode (LED) is li

20、t to indicate the power is on. The signal Q1 is sent to the setting terminal of dff2 to set terminal Q2 at high level. The high level Q2 will set circular_shift_r into the parallel input address code mode. At this time, the outer transistor N2 is at saturation state and N3 at cut-off state. This mak

21、es the sending circuit at a passive state, therefore, the circuit will not work. Hence, the circuit does not emit carrier wave if there is no case, and it is at low consumable power state.Once some cases appear, the switch K1 is on. The terminal D of the dff1 turns to high level immediately, and the

22、 output Q1of dff1 is set to high level at the rising edge of the clock pulse. It makes the setting terminal s of dff2 at high level too. The dff2 now is at normal working state. After delaying by module delay1, the former edge of the Q1 pulse will trigger dff2 to output low voltage, which will make

23、the transistor N2 off, N3 on, and the delays normally open contact will be closed. The electric power supply to the sending circuit is on, and the circuit begins to work normally. Simultaneously, if Q2 is at logic 0, circular_shift_r will be change to serial shift state and export address signals. W

24、hen the address code is 0, the output of MUX will be f2. And when the address code is 1, the output will be f1. Terminals f2 and f1 act as the modulation signal for modulating the carrier wave. In this way, the address code is sent out at the first cycle of the low frequency oscillator. At the secon

25、d cycle it stops sending in order to give other stand-off a period of time to send. After the third cycle, repeat the procedure above. From the discussion above, we have the conclusion that the encoding and control circuit have the function to display when the power is on, time delay for human to le

26、ave the spot, low power cost mode for waiting case, discontinuity sending and FSK modulating etc. It is more flexible and has more functions than many encoder ASIC. III.THE CONFIGURATION AND PRINCIPLE OF THE RECEIVING SYSTEM Set in guardhouse, a set of wireless receiver takes charge of monitoring al

27、l stand-off areas. The principle of the wireless receiver is show following. Passing by the low pass filter, the received modulation signal is sent into the high frequency common-emitter and common-base configuration cascade amplifier for amplifying. Then the signal is sent to the intermediate frequ

28、ency modulation amplifier via the dual tuning circuit, i.e. sent into the input terminal (16th pin) of an ASIC chip (MC3372) to do mixing. The oscillate frequency of the local oscillator circuit is 455KHz higher than the received signal. Delivering to the first pin of the chip MC3372, the signal wil

29、l mix with the external signal to get 455KHz intermediate frequency signal. After filtering, the intermediate frequency signal is first delivered to the 8th MC3372 pin to do frequency detection, and second amplified by an inner low frequency amplifier of the chip MC3372, then the 9th pin exports the

30、 baseband signal. Amplified by a low frequency single transistor, the baseband signal is rectified by two steps Schmitt gates (CD4584) to turn into a FSK signal, which will be sent into pin 3.0 of MCS to be decoded. MCS in this system is chip 89C51, which joins an outer 12MHZ crystal oscillator. Its

31、 timer T1 act as a baud rate generator in mode 2, and SMOD=1,300 baud/sec. serial port is selected in mode 1, which means an asynchronous communication mode, 10 bit per frame in which the lower 7 bits of the 8 data bit is the address code, and the 8th acts as the parity check bit. The system uses ev

32、en check. When receiving an address code, the MCS firstly performs parity check. If it is correct ,then ,the MCS compare their value and takes out 7 bits address code and stores it into data buffer in memory. These procedures repeat 3 times in order to identify the 3 address codes. If the 3 address codes are the same, the MCS will confirm that the receiving address signal is an effective alarm signal, that is to say, the address code is not a noise signal. It then triggers the alarm circuit to send the alarm sound. At the same time, the code number will display on the