SPI总线.docx

1、SPI总线SPI - Serial Peripheral Interface同步串行外设接口(SPI)是由摩托罗拉公司开发的全双工同步串行总线，该总线大量用在与EEPROM、ADC、FRAM和显示驱动器之类的慢速外设器件通信。SPI（Serial Peripheral Interface）是一种串行串行同步通讯协议，由一个主设备和一个或多个从设备组成，主设备启动一个与从设备的同步通讯，从而完成数据的交换。SPI 接口由SDI（串行数据输入），SDO（串行数据输出），SCK（串行移位时钟），CS（从使能信号）四种信号构成，CS 决定了唯一的与主设备通信的从设备，如没有CS 信号，则只能存在一个从

2、设备，主设备通过产生移位时钟来发起通讯。通讯时，数据由SDO 输出，SDI 输入，数据在时钟的上升或下降沿由SDO 输出，在紧接着的下降或上升沿由SDI 读入，这样经过8/16 次时钟的改变，完成8/16 位数据的传输。总线协议该总线通信基于主-从(所有的串行的总线均是这样，USB，IIC，SPI等)配置，而且下面提到的方向性的操作合指代全部从主设备的角度说得。它有以下4个信号：MOSI:主出/从入MISO:主入/从出SCK:串行时钟SS:从属选择；芯片上“从属选择”(slave-select)的引脚数决定了可连到总线上的器件数量。在SPI传输中，数据是同步进行发送和接收的。数据传输的时钟基于

3、来自主处理器的时钟脉冲(好像也可以是IO上的电平的模拟时钟)，摩托罗拉没有定义任何通用SPI的时钟规范。然而，最常用的时钟设置基于时钟极性(CPOL)和时钟相位(CPHA)两个参数，CPOL定义SPI串行时钟的活动状态，而CPHA定义相对于SO-数据位的时钟相位。CPOL和CPHA的设置决定了数据取样的时钟沿。数据方向和通信速度SPI传输串行数据时首先传输最高位。波特率可以高达5Mbps，具体速度大小取决于SPI硬件。例如，Xicor公司的SPI串行器件传输速度能达到5MHz。SPI总线接口及时序SPI总线包括1根串行同步时钟信号线以及2根数据线。SPI模块为了和外设进行数据交换，根据外设工作

4、要求，其输出串行同步时钟极性和相位可以进行配置，时钟极性（CPOL）对传输协议没有重大的影响。如果CPOL=0，串行同步时钟的空闲状态为低电平；如果CPOL=1，串行同步时钟的空闲状态为高电平。时钟相位（CPHA）能够配置用于选择两种不同的传输协议之一进行数据传输。如果CPHA=0，在串行同步时钟的第一个跳变沿（上升或下降）数据被采样；如果CPHA=1，在串行同步时钟的第二个跳变沿（上升或下降）数据被采样。SPI主模块和与之通信的外设音时钟相位和极性应该一致。SPI接口时序如图3、图4所示。SPI是一个环形总线结构，由ss（cs）、sck、sdi、sdo构成，其时序其实很简单，主要是在sck的

5、控制下，两个双向移位寄存器进行数据交换。假设下面的8位寄存器装的是待发送的数据10101010，上升沿发送、下降沿接收、高位先发送。那么第一个上升沿来的时候数据将会是sdo=1；寄存器=0101010x。下降沿到来的时候，sdi上的电平将所存到寄存器中去，那么这时寄存器=0101010,sdi，这样在8个时钟脉冲以后，两个寄存器的内容互相交换一次。这样就完成里一个spi时序。例子假设主机和从机初始化就绪：并且主机的sbuff=0xaa（10101010），从机的sbuff=0x55(01010101)，下面将分步对spi的8个时钟周期的数据情况演示一遍:假设上升沿发送数据. 脉冲(SCLK)主

6、机sbuff(主端发送)从机sbuff(主端接受)sdi串行输入到主端sdo串行输出从主端01010101001010101001上0101010x1010101x011下0101010010101011012上1010100x0101011x102下1010100101010110103上0101001x1010110x013下0101001010101101014上1010010x0101101x104下1010010101011010105上0100101x1011010x015下0100101010110101016上1001010x0110101x106下10010101011010

7、10107上0010101x1101010x017下0010101011010101018上0101010x1010101x108下010101011010101010这样就完成了两个寄存器8位的交换，上面的上表示上升沿、下表示下降沿，sdi、sdo相对于主机而言的。其中ss引脚作为主机的时候，从机可以把它拉底被动选为从机，作为从机的是时候，可以作为片选脚用。根据以上分析，一个完整的传送周期是16位，即两个字节，因为，首先主机要发送命令过去，然后从机根据主机的命令准备数据，主机在下一个8位时钟周期才把数据读回来，主机产生时钟SCLK，而数据又必须依靠边沿启动才能传送。SPI 总线是Motoro

8、la公司推出的三线同步接口，同步串行3线方式进行通信:一条时钟线SCK，一条数据输入线MOSI，一条数据输出线MISO;用于CPU与各种外围器件进行全双工、同步串行通讯。SPI主要特点有:可以同时发出和接收串行数据;可以当作主机或从机工作;提供频率可编程时钟;发送结束中断标志;写冲突保护;总线竞争保护等。图3示出SPI总线工作的四种方式，其中使用的最为广泛的是SPI0和SPI3方式(实线表示): 图2 SPI总线四种工作方式SPI模块为了和外设进行数据交换，根据外设工作要求，其输出串行同步时钟极性和相位可以进行配置，时钟极性（CPOL）对传输协议没有重大的影响。如果CPOL=0，串行同步时钟的

9、空闲状态为低电平；如果CPOL=1，串行同步时钟的空闲状态为高电平。时钟相位（CPHA）能够配置用于选择两种不同的传输协议之一进行数据传输。如果CPHA=0，在串行同步时钟的第一个跳变沿（上升或下降）数据被采样；如果CPHA=1，在串行同步时钟的第二个跳变沿（上升或下降）数据被采样。SPI主模块和与之通信的外设音时钟相位和极性应该一致。SPI接口时序如图3、图4所示。PrefaceWith this article, the possibilities of serial communication with peripheral devices via SPI (Serial Periphe

10、ral Interface) will be discussed. More and more serial bus systems are preferred instead of a parallel bus, because of the simpler wiring. As the efficiency of serial buses increases, the speed advantage of the parallel data transmission gets less important. The clock frequencies of SPI devices can

11、go up to some Megahertz and more. There are a lot of application where a serial transmission is perfectly sufficient. The usage of SPI is not limited to the measuring area, also in the audio field this type of transmission is used.The SPI (this name was created by Motorola) is also known as Microwir

12、e, trade mark of National Semiconductor. Both have the same functionality. There are also the extensions QSPI (Queued Serial Peripheral Interface) and MicrowirePLUS.The popularity of other serial bus systems like I2C, CAN bus or USB shows, that serial buses get used more and more.Below is a list of

13、SPI devices. However this list neither claims to be complete nor is the availablability of the listed components guaranteed. In addition there is a list of manufacturers with the type of SPI components they produce.Martin Schwerdtfeger, 06/2000The PrincipleThe Serial Peripheral Interface is used pri

14、marily for a synchronous serial communication of host processor and peripherals. However, a connection of two processors via SPI is just as well possible and is described at the end of the chapter.In the standard configuration for a slave device (see illustration 1), two control and two data lines a

15、re used. The data output SDO serves on the one hand the reading back of data, offers however also the possibility to cascade several devices. The data output of the preceding device then forms the data input for the next IC.Illustration 1: SPI slaveThere is a MASTER and a SLAVE mode. The MASTER devi

16、ce provides the clock signal and determines the state of the chip select lines, i.e. it activates the SLAVE it wants to communicate with. CS and SCKL are therefore outputs.The SLAVE device receives the clock and chip select from the MASTER, CS and SCKL are therefore inputs.This means there is one ma

17、ster, while the number of slaves is only limited by the number of chip selects.A SPI device can be a simple shift register up to an independent subsystem. The basic principle of a shift register is always present. Command codes as well as data values are serially transferred, pumped into a shift reg

18、ister and are then internally available for parallel processing. Here we already see an important point, that must be considered in the philosophy of SPI bus systems: The length of the shift registers is not fixed, but can differ from device to device. Normally the shift registers are 8Bit or integr

19、al multiples of it. Of course there also exist shift registers with an odd number of bits. For example two cascaded 9Bit EEPROMs can store 18Bit data.If a SPI device is not selected, its data output goes into a high-impedance state (hi-Z), so that it does not interfere with the currently activated d

20、evices. When cascading several SPI devices, they are treated as one slave and therefore connected to the same chip select.Thus there are two meaningful types of connection of master and slave devices. illustration 2 shows the type of connection for cascading several devices.Illustration 2: Cascading

21、 several SPI devicesIn illustration 2 the cascaded devices are evidently looked at as one larger device and receive therefore the same chip select. The data output of the preceding device is tied to the data input of the next, thus forming a wider shift register.If independent slaves are to be conne

22、cted to a master an other bus structure has to be chosen, as shown in illustration 3. Here, the clock and the SDI data lines are brought to each slave. Also the SDO data lines are tied together and led back to the master. Only the chip selects are separately brought to each SPI device.Illustration 3

23、: Master with independent slavesLast not least both types may be combined.It is also possible to connect two micro controllers via SPI. For such a network, two protocol variants are possible. In the first, there is only one master and several slaves and in the second, each micro controller can take

24、the role of the master. For the selection of slaves again two versions would be possible but only one variant is supported by hardware. The hardware supported variant is with the chip selects, while in the other the selection of the slaves is done by means of an ID packed into the frames. The assign

25、ment of the IDs is done by software. Only the selected slave drives its output, all other slaves are in high-impedancd state. The output remains active as long as the slave is selected by its address.The first variant, named single-master protocol, resembles the normal master-slave communication. Th

26、e micro controller configured as a slave behaves like a normal peripheral device.The second possibility works with several masters and is therefore named multi-master protocol. Each micro processor has the possibility to take the roll of the master and to address another micro processor. One control

27、ler must permanently provide a clock signal. The MC68HC11 provides a harware error recognition, useful in multiple-master systems. There are two SPI system errors. The first occurs if several SPI devices want to become master at the same time. The other is a collision error that occurs for example w

28、hen SPI devices work with with different polarities. More details can be found in the MC68HC11 manual.Data and Control Lines of the SPIThe SPI requires two control lines (CS and SCLK) and two data lines (SDI and SDO). Motorola names these lines MOSI (Master-Out-Slave-In) and MISO (Master-In-Slave-Ou

29、t). The chip select line is named SS (Slave-Select).With CS (Chip-Select) the corresponding peripheral device is selected. This pin is mostly active-low. In the unselected state the SDO lines are hi-Z and therefore inactive. The master decides with which peripheral device it wants to communicate. Th

30、e clock line SCLK is brought to the device whether it is selected or not. The clock serves as synchronization of the data communication.The majority of SPI devices provide these four lines. Sometimes it happens that SDI and SDO are multiplexed, for example in the temperature sensor LM74 from Nationa

31、l Semiconductor, or that one of these lines is missing. A peripheral device which must or can not be configured, requires no input line, only a data output. As soon as it gets selected it starts sending data. In some ADCs therefore the SDI line is missing (e.g. MCCP3001 from Microchip).There are als

32、o devices that have no data output. For example LCD controllers (e.g. COP472-3 from National Semiconductor), which can be configured, but cannot send data or status messages.SPI ConfigurationBecause there is no official specification, what exactly SPI is and what not, it is necessary to consult the data sheets of the