1、使用labview fpga模块开发可编程自动化控制器外文文献及翻译大学论文使用LabVIEW FPGA模块开发可编程自动化控制器学院: 通信与电子工程学院 班级: 电子071 学号: 姓名: Building Programmable Automation Controllers with LabVIEW FPGAOverviewProgrammable Automation Controllers (PACs) are gaining acceptance within the industrial control market as the ideal solution for appl
2、ications that require highly integrated analog and digital I/O, floating-point processing, and seamless connectivity to multiple processing nodes. National Instruments offers a variety of PAC solutions powered by one common software development environment, NI LabVIEW. With LabVIEW, you can build cu
3、stom I/O interfaces for industrial applications using add-on software, such as the NI LabVIEW FPGA Module. With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instruments delivers an intuitive, accessible solution for incorporating the flexibility and customizability of FPGA
4、 technology into industrial PAC systems. You can define the logic embedded in FPGA chips across the family of RIO hardware targets without knowing low-level hardware description languages (HDLs) or board-level hardware design details, as well as quickly define hardware for ultrahigh-speed control, c
5、ustomized timing and synchronization, low-level signal processing, and custom I/O with analog, digital, and counters within a single device. You also can integrate your custom NI RIO hardware with image acquisition and analysis, motion control, and industrial protocols, such as CAN and RS232, to rap
6、idly prototype and implement a complete PAC system.Table of Contents1. Introduction 2. NI RIO Hardware for PACs 3. Building PACs with LabVIEW and the LabVIEW FPGA Module 4. FPGA Development Flow 5. Using NI SoftMotion to Create Custom Motion Controllers 6. Applications 7. Conclusion Introduction You
7、 can use graphical programming in LabVIEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices. RIO technology, the merging of LabVIEW graphical programming with FPGAs on NI RIO hardware, provides a flexible platform for creating sophisticated measureme
8、nt and control systems that you could previously create only with custom-designed hardware.An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can configure and reconfigure the
9、 logic on FPGAs for your specific application. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. The flexible, software-programmable architecture of FPGAs offer benefits suc
10、h as high-performance execution of custom algorithms, precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific comp
11、uter hardware. While FPGAs are often used in industrial control products, FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complex design tools used more by hardware design engineer
12、s than by control engineers.Withinthetest-fixturethetxoutputofthetransmittermoduleisloopedbacktotherxinputofthereceivermodule.Thisallowsthetransmittermoduletobeusedastestsignalgeneratorforthereceivermodule.Datacanbewritteninparallelformattothetransmittermoduleandloopedbackinserialformattotherxinputo
13、fthereceivermodule,anddatareceivedcanfinallybereadoutinparallelformatfromthereceivermodule.InordertoautomatethetestingoftheUARTasmuchaspossible,treeindependentVerilogtaskswerewrittenasfollows.TheVerilog task“write_to_transmitter”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatawritese
14、quencetothetransmittermodule.Datathatarewrittentothetransmitteruponexecutionofthe“write_to_transmitter”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“read_out_receiver”holdsallnecessarystatementsrequiredtogenerateasingle paralleldatareadoutsequencefromthereceivermodule.Datat
15、hatarereadoutofthereceiveruponexecutionofthe“read_out_receiver”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“compare_data”holdsallnecessarystatementsrequiredtocomparethepreviousdatawrittentothetransmittermodule,to thecorrespondingandmostrecentdatareceivedandreadoutfromthere
16、ceivermodule.Ifanydiscrepancyoccurs,the“compare_data”taskflagsforanerrorbywritingoutthedatavaluesthatwerewrittentothetransmittermodule,aswellasthecorrespondingdatavaluesthatwerereceivedbyandreadoutfromthereceivermodule.Thesimulationisimmediatelystoppedbythe“compare_data”taskifanydiscrepancyoccurs.Be
17、sidesthetreeabovementionedVerilogtasks,thetest-fixtureholdsthestatementstogeneratethemclkx16,themasterresetsignalsaswellasthe“txtorx”loopbackfeature.Thestatementsareconsideredtrivial,andwillnotbeillustratedhere,butcanbereferredtowithinthetest-fixtureitself.Thecoreofthetest-fixtureisabehaviorallevel“
18、forloop”thatexecutesthetreeabovementionedVerilogtasksinordertowriteallpossibledatacombinationstothetransmitterandverifythatsamedatagetsproperlyreceivedbythereceiver.Theforloopisshowed below in figure 21.Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout(bidirectiona
19、l),andcanbereferredtointable1.Nexttothe specificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithinth
20、eVerilog“always”block,oftenuseforsequentiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescription
21、languageallowsusto describethefunctionofthetransmitterinamorebehavioralmanner,ratherthanfocusonitsactualimplementationatgatelevelInsoftwareprogramminglanguage, functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandta
22、sksasconstructs,analogoustosoftwarefunctionsandprocedures.AVerilogfunctionand taskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakest
23、hedesigneasiertoreadandcertainlymaintain.AVerilogfunction canhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shi
24、ft”modeWith the LabVIEW FPGA Module and NI RIO hardware, you now can use LabVIEW, a high-level graphical development environment designed specifically for measurement and control applications, to create PACs that have the customization, flexibility, and high-performance of FPGAs. Because the LabVIEW
25、 FPGA Module configures custom circuitry in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically. Figure 1 illustrates many of the NI RIO devices that you can configure using the LabVIEW FPGA Module.Figure 1. LabVIEW FPGA VI Block Diagr
26、am and RIO Hardware Platforms NI RIO Hardware for PACs Historically, programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools, which require overcoming a very steep learning curve. With the LabVIEW FPGA Module, NI has opened FPGA technology
27、to a broader set of engineers who can now define FPGA logic using LabVIEW graphical development. Measurement and control engineers can focus primarily on their test and control application, where their expertise lies, rather than the low-level semantics of transferring logic into the cells of the ch
28、ip. The LabVIEW FPGA Module model works because of the tight integration between the LabVIEW FPGA Module and the commercial off-the-shelf (COTS) hardware architecture of the FPGA and surrounding I/O components.National Instruments PACs provide modular, off-the-shelf platforms for your industrial con
29、trol applications. With the implementation of RIO technology on PCI, PXI, and Compact Vision System platforms and the introduction of RIO-based CompactRIO, engineers now have the benefits of a COTS platform with the high-performance, flexibility, and customization benefits of FPGAs at their disposal
30、 to build PACs. National Instruments PCI and PXI R Series plug-in devices provide analog and digital data acquisition and control for high-performance, user-configurable timing and synchronization, as well as onboard decision making on a single device. Using these off-the-shelf devices, you can extend your NI PXI or PCI industrial control system to include high-speed discrete and analog control, custom sensor interfaces, and precise timing and control. NI CompactRIO, a platform centered on RIO technology, provides a small, industrially rugged, modular PAC platfo
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