超大规模集成电路第九次作业秋段成华.docx

1、超大规模集成电路第九次作业秋段成华Assignment 91. Design an 8-bit up and down synchronous counter in VHDL with the following features:(1)The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state).(2)The counter is with an asynchronous reset that assigns a s

2、pecific initial value for counting.(3)The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operatio

3、n is in process the counter operation is prohibited.(4)Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used.Synthesize the design. Create a set of reasonable input waveforms for your design and complete both behavioral and post-place&route simulations with internal signals a

4、nd/or variables included in waveform or list windows. Solution:代码如下：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VCo

5、mponents.all;entity count_8_bidir is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; load : in STD_LOGIC; enable : in STD_LOGIC; cnt : inout STD_LOGIC_VECTOR (7 downto 0); end count_8_bidir;architecture Behavioral of count_8_bidir issignal cnt_in: STD_LOGIC_VECTOR (7 downto 0); signal cnt_out: STD_LO

6、GIC_VECTOR (7 downto 0);begin pro0:process(oe,cnt_out,cnt) begin if(load=1)then cnt Z); cnt_in = cnt; else cnt = cnt_out; end if; end process; pro1:process(clk,rst) begin if(rst=1)then cnt_out 0); elsif rising_edge(clk)then if(load=1)then cnt_out = cnt_in; elsif(enable=1)then cnt_out = cnt_out + 1;

7、else cnt_out oe, clk = clk, rst = rst, load = load, enable = enable, cnt = cnt ); - Clock process definitions clk_process :process begin clk = 0; wait for clk_period/2; clk = 1; wait for clk_period/2; end process; - Stimulus process stim_proc: process begin rst=1; load=0; enable=1; cntZ); wait for 1

8、00 ns; rst=0; wait for 500 ns; load=1; cnt=11000000; wait for 200 ns; load=0; cntZ); wait for 500 ns; enable=0; wait for 500 ns; rst=1; wait; end process;END;根据TestBench的激励可以看出：进入程序之后，首先复位且load=0，这时cnt_out从0开始做加法运算，当计数到5之后，load=1把cnt变成了输入，并且给其赋了11000000（转化为整数为192），并且在上升沿条件下送到cin_out，此时cin_out=192；在加

9、载该值之后，200ns之后将load=0将cnt变为输出，此时cnt开始从192向上计数，记了经过500ns记到了197，然后遇到了enable=0，开始做减法，经过500ns，cnt变为192，随后rst=1，将cnt清0，到此结束，功能验证为正确。后仿真波形如上所示，与行为仿真的差别，就是前面几百ps增加了一个Unknown状态（没有初始化的缘故），同时cnt相对于时钟沿有延迟。2. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA.(1)Sy

10、nthesize and verify (simulate) the VHDL design of the FIFOs;综合后的RTL schematic和功能仿真后的结果分别如下图1和图2所示。图1图2(2)For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells) and PTs (product terms) are needed? Which parameter is critical to the maximum internal clock working frequency? Try to find

11、out this critical parameter and its corresponding circuit path.设置芯片为CoolRunner XPLA3 CPLDS系XCR3512XL-7-PQ208，速度为-7，综合后报告分析如下 图3为CPLD综合报告：从报告中可以知道一共使用了87个MCs，占总体的17%，使用了208个PTs，占总体的14%，选这个型号似乎有点大材小用啊，不过资源很足够，满足设计的需求。图4为CPLD时间报告：由图 4可知，时钟的最小周期为8.6ns，受clock to setup影响最大，故关键路径为tcyc。延时为8.6ns，时钟的工作频率为116.

12、279MHz。图3图4(3)For FPGA implementation (place and route) of the FIFOs, how many LBs (logic blocks)? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.设置芯片为更换芯片型号为Spartan3- xc3s200-5pq208,速度为-5，其综合报告如

13、下图5为FPGA综合报告：图5图6为Spartan3 datasheet图6图7由上图知，对于选择的器件，其logic cell为4320,CLB 有24X20=480个，每个CLB包含4个slice,而对于我们的程序，一共使用了66个slice，占总数的百分之三（总slice共计1920个），故使用的CLB数为66/4=16.5，即使用了17个。由图 7可知，时钟的最小周期为5.078ns，受clock to setup影响最大，时钟的工作频率为196.927MHz。(4)Try to synthesize again the design with timing constraints a

14、nd compare with its former counterparts. You will create the timing constraint yourself and add it to your project. Please refer to the following graphic interface of ISE:图8为 timing constrain设置图；图9为没有设置时序约束时的报告；图10为设置CLK周期约束为5ns时的报告；图11为设置CLK周期约束为4.5ns时的报告；图 12 设置clk周期约束为4ns时的报告图 13 设置clk周期约束为3.5ns时

15、的报告图8图9图10图11图12图133. For the VHDL model given below (Code List Two), there may be some design errors in it. Some warning(s) and/or error(s) information may be issued when synthesizing it. Try to find out such design errors and correct them.仿真后无错误，有两个警告如下图：图14(1) 程序中，输入端口rd没有使用到，其作用被oe所取代，因此可以将rd信号去

16、掉，用oe来表示其功能，且不影响整个系统的设计。(2) 程序中输入信号端口en也未被使用，因为直接在fifo(wrptr)中取得了写地址的值，因此信号en也应去掉。(3) 语句dmuxout=fifo(wrptr); 应改为dmuxout=fifo(rdptr); 因为这时是读寄存器里的值，应该由读地址指针rdptr来指定应该读取哪个寄存器的值。改进后加入激励得到图15的输出波形。图158X9 FIFO BUFFER DESIGN EXAMPLES1# VHDL CODE LIST:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LO

17、GIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fifo89 is Port ( clk : in std_logic; rst : in std_logic; rd : in std_logic; wr : in std_logic; rdinc : in std_logic; wrinc : in std_logic; rdptrclr : in std_logic; wrptrclr : in std_logic; data_in : in std_logic_vector(8 downto 0); data_out : out

18、std_logic_vector(8 downto 0);end fifo89;- clk: used to synchronize the buffers;- rst: reset the buffers- rd: when valid, the output buffers are enabled;- wr: when valid, write register with 9-bit width is permitted; - rdinc: read counter enabled;- wrinc: write counter enabled;- rdptrclr: reset read

19、counter, pointing to the first register for- read purpose;- wrptrclr: reset write counter, pointing to the first register for- write purpose;- data_in: data inputs with 9-bit width to the FIFOs;- data_out: data outputs with 9-bit width from the FIFOs.architecture Behavioral of fifo89 is type fifo_ar

20、ray is array(7 downto 0) of std_logic_vector(8 downto 0); signal fifo: fifo_array; signal wrptr, rdptr: std_logic_vector(2 downto 0); signal en: std_logic_vector( 7 downto 0); signal dmuxout: std_logic_vector(8 downto 0);begin- fifo register_array:reg_array: process (rst, clk) begin if rst = 1 then

21、for i in 7 downto 0 loop fifo(i) 0); - aggregate end loop; elsif (clkevent and clk = 1) then if wr = 1 then for i in 7 downto 0 loop if en(i) = 1 then fifo(i) = data_in; else fifo(i) = fifo(i); end if; end loop; end if; end if; end process;- read pointerread_count: process (rst, clk) begin if rst =

22、1 then rdptr 0); elsif (clkevent and clk = 1) then if rdptrclr = 1 then rdptr 0); elsif rdinc = 1 then rdptr = rdptr + 1; end if; end if; end process;- write pointerwrite_count: process (rst, clk) begin if rst = 1 then wrptr 0); elsif (clkevent and clk = 1) then if wrptrclr = 1 then wrptr 0); elsif

23、wrinc = 1 then wrptr = wrptr + 1; end if; end if; end process;- 8:1 output data muxwith rdptr select dmuxout = fifo(0) when 000, fifo(1) when 001, fifo(2) when 010, fifo(3) when 011, fifo(4) when 100, fifo(5) when 101, fifo(6) when 110, fifo(7) when others;- FIFO register selector decoderwith wrptr

24、select en = 00000001 when 000, 00000010 when 001, 00000100 when 010, 00001000 when 011, 00010000 when 100, 00100000 when 101, 01000000 when 110, 10000000 when others;- three-state control of outputsthree_state: process (rd, dmuxout) begin if rd = 1 then data_out = dmuxout; else data_out Z); end if;

25、end process;end Behavioral;2# VHDL CODE LIST:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fifoxy is generic (wide: integer := 8); - width is 8 + 1 Port ( clk : in std_logic; rst : in std_logic; oe: in std_logic; rd : in std_logic; wr : in std_logic; rdinc : in std_logic; wrinc : in std_logic;