EDA期末大作业设计.docx

1、EDA期末大作业设计宁波理工学院 EDA课程设计报告 题 目 简易电子琴 组 员 王维婷（3110403128） 郑雅亿（3110403131） 专业班级 电子信息工程112班 1、实验目的1.学习利用数控分频器、键盘实验。2.理解PS/2键盘的基本原理。2、实验原理本实验利用键盘的数字按键部分来控制电子琴的C调，DO RA,MI,FA,SO,LA,SI,分别用0,1,2,3,4，5,6，7来进行控制。们使用了键盘的介入来进行控制。组成乐曲的每个音符的发音频率值及其持续的时间是乐曲能连续演奏所需的2个基本要素，首先让我们来了解音符与频率的关系。乐曲的12平均率规定：每2个八度音(如简谱中的中音

2、1与高音1)之间的频率相差1倍。在2个八度音之间，又可分为12个半音，每2个半音的频率比为。另外，音符A(简谱中的低音6)的频率为440Hz，音符B到C之间、E到F之间为半音，其余为全音。由此可以计算出简谱中从低音1至高音1之间每个音符的频率，如图所示。 简谱中音符与频率的关系如图所示，为PS/2键盘的接口引脚图。下图为PS/2键盘的通信时序图。主系统由4个模块组成：TOP是顶层设计文件，其内部有三个功能模块：Tone.VHD、Speaker.VHD、enc16_4.VHD.、PS2VHDL.VHD、clkdiv10.VHD、clkdiv50.VHD以及PULSE12.VHD模块TONE是音阶

3、发生器，当4位发声控制输入INDEX中某一位为高电平时，则对应某一音阶的数值将从端口TONE输出，作为获得该音阶的分频预置值；同时由CODE输出对应该音阶简谱的显示数码，如5，并由HIGH输出指示音阶高8度显示。由例6-28可见，其语句结构只是类似与真值表的纯组合电路描述，其中的音阶分频预置值，如Tone Y Y Y Y Y Y Y Y Y Tone = CONV_STD_LOGIC_VECTOR(2047,11);-CONV_STD_LOGIC_VECTOR(139,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LO

4、GIC_VECTOR(347,11); CODE = CONV_STD_LOGIC_VECTOR(2,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(533,11); CODE = CONV_STD_LOGIC_VECTOR(3,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(615,11);CODE = CONV_STD_LOGIC_VECTOR(4,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(773,11); CODE = CONV_STD_LOGIC_VECTOR(5,4); HIGH Tone =

5、CONV_STD_LOGIC_VECTOR(912,11); CODE = CONV_STD_LOGIC_VECTOR(6,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1036,11); CODE = CONV_STD_LOGIC_VECTOR(7,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1092,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1197,11); CODE = CONV_STD_LOGIC_VECTOR(1,4

6、); HIGH Tone = CONV_STD_LOGIC_VECTOR(1290,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1372,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1410,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1480,11); CODE = CONV_STD_

7、LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1542,11); CODE Tone = CONV_STD_LOGIC_VECTOR(1622,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(1728,11); CODE = CONV_STD_LOGIC_VECTOR(1,4); HIGH Tone = CONV_STD_LOGIC_VECTOR(2047,11); CODE = CONV_STD_LOGIC_VECTOR(0,4);

8、HIGH = 0; END CASE; END PROCESS;END;PS2VHDL- VHDL library Declarations LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;- The Entity Declarations ENTITY PS2VHDL IS PORT(ClkFilter: IN STD_LOGIC;-1MHzRESET: IN STD_LOGIC;KBDATA: IN STD_LOGIC; KBCLK:

9、IN STD_LOGIC;EOC: OUT STD_LOGIC;PDATA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END PS2VHDL;- The Architecture of Entity Declarations ARCHITECTURE Behavioral OF PS2VHDL ISSIGNAL spdata: STD_LOGIC_VECTOR(10 DOWNTO 0);SIGNAL TT: STD_LOGIC;SIGNAL cnt8: INTEGER RANGE 0 TO 10;BEGIN- Optimize PROCESS( RESET, KBCL

10、K, ClkFilter )VARIABLE Count : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF(RESET = 0 OR KBCLK = 0)THEN TT 0);ELSIF( ClkFilterEVENT AND ClkFilter = 1 ) THEN IF( Count 1100 ) THEN Count := Count + 1; TT = 0;ELSECount := 1100; TT = 1;END IF; END IF; END PROCES- Recevie Recevie: PROCESS( RESET, TT, KBDATA, spd

11、ata, cnt8 )BEGINIF RESET = 0 THEN cnt8 = 0; spdata 0);ELSIF TTevent AND TT = 0 THEN IF( cnt8 10 ) THEN spdata(cnt8) = KBDATA;cnt8 = cnt8 + 1; ELSE cnt8 = 0; END IF; END IF; END PROCESS; - End of recevie PROCESS( RESET, cnt8 )BEGINIF RESET = 0 THEN EOC = 0;ELSIF cnt8 /= 0 THEN EOC = 1;ELSE EOC = 0;EN

12、D IF; END PROCESS; -PDATA = spdata( 8 downto 1 );END Behavioral; clkdiv10-占空比为1：1的任意偶数倍分频Library IEEE;Use IEEE.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity clkdiv10 is Port( clk: in std_logic; clk_out: out std_logic);end clkdiv10;architecture arch of clkdiv10 issignal count : integer ra

13、nge 0 to 49; -分频倍数-1beginprocess (clk) -分频器begin if clkevent and clk=1 then if count=counthigh then count=0; else countcounthigh/2 then clk_out=1; else clk_out=0; end if; end if;end process;-count_out = count;end arch;clkdiv50-占空比为1：1的任意偶数倍分频Library IEEE;Use IEEE.std_logic_1164.all;Use ieee.std_logi

14、c_unsigned.all;Entity clkdiv50 is Port( clk: in std_logic;-count_out :out integer range 0 to 119; clk_out: out std_logic);end clkdiv50;architecture arch of clkdiv50 issignal count : integer range 0 to 49; -分频倍数-1beginprocess (clk) -分频器begin if clkevent and clk=1 then if count=counthigh then count=0;

15、 else countcounthigh/2 then clk_out=1; else clk_out=0; end if; end if;end process;-count_out = count;end arch;PULSE12LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PULSE12 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(10 DOWNTO 0); FOUT : OUT STD_LOGIC );END;

16、ARCHITECTURE one OF PULSE12 ISSIGNAL FULL : STD_LOGIC;SIGNAL CNT8 : STD_LOGIC_VECTOR(10 DOWNTO 0);SIGNAL CNT2 : STD_LOGIC;BEGINP_REG: PROCESS(CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN IF CNT8 = 11111111111 THEN CNT8 = D; -当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL = 1; -同时使溢出标志信号FULL输出为高电平 ELSE CNT8 = CNT8 +

17、1; -否则继续作加1计数 FULL = 0; -且输出溢出标志信号FULL为低电平 END IF; END IF; END PROCESS P_REG ; P_DIV: PROCESS(FULL) BEGIN IF FULLEVENT AND FULL = 1 THEN CNT2 = NOT CNT2; -如果溢出标志信号FULL为高电平，D触发器输出取反 END IF;END PROCESS P_DIV ;FOUT = CNT2;END;4、实验总结 通过本次实验，使我对使用VHDL编写模块来实现音乐播放有了更深一步的了解，在本次实验中，在原先的基础上加入了播放暂停的功能，并更换了歌曲。使仿真更具有功能性，并且更加熟悉了利用数控分频器设计硬件，受益匪浅。