Systemofsystems approach for interdependent critical infrastructures.docx

1、Systemofsystems approach for interdependent critical infrastructures无线通信系统工程师北京信威通信技术股份有限公司查看公司简介粉丝团(16)|公司行业：通信/电信/网络设备通信/电信运营、增值服务公司性质：民营公司公司规模：500人以上比比你的竞争力 发布日期：2011-04-08工作地点：北京-海淀区招聘人数：1工作年限：一年以上语言要求：英语熟练学历：硕士职位描述 岗位职责： 1、组织McWiLL系统的空口协议中关键算法、功能的研究、制定和验证；跟踪收集在应用中的问题、建议，并进行相关维护升级； 2、进行McWiLL系统的

2、系统级、链路级的仿真工作，为McWiLL的算法设计、功能方案等提供理论依据。任职资格： 1、硕士及以上学历，无线通信或数字信号处理专业； 2、熟练使用matlab和C/Cpp进行仿真或相关接口函数编写，深刻理解并有较强3G/4G无线通信系统设计或实现经验，良好的中英文口语和读写能力，现场测试/诊断问题的能力； 3、较强的沟通协调能力、口头表达能力以及文字功底； 4、较好的英语水平，6级以上水平。比比你的竞争力 收藏 推荐给朋友 该公司其他职位 打印 粉丝团(16)|信威通信产业集团（以下简称“集团”）在世界通信领域具备着巨大的实力和崇高的地位。集团以“自主创新、报效国家”为己任。以技术、市场、

3、资本相融合；以客户、员工、企业相融合；以企业、国家利益需求、人类社会进步相融合为统筹体系。打造技术研发、产品制造、销售服务、建设运营的完整通信信息产业链。以国防军工、空天信息、三网物联、公共运营、公共安全、水电交通等六大主要板块为核心市场。在国际、国内多个行业领域名列第一。北京信威通信技术股份有限公司（以下简称“北京信威”）是集团核心企业，北京信威成立于1995年11月，目前公司注册资本2.14亿元人民币，价值100亿元人民币以上。十六年来一直致力于我国自主知识产权的无线通信技术的研发和产业化，创立了SCDMA（Synchronous Code Division Multiple Access

4、 同步码分多址，中国通信标准）、TD-SCDMA（Time Division-Synchronous Code Division Multiple Access 时分同步码分多址，ITU国际标准）、McWiLL（Multicarrier Wireless Information Local Loop 多载波无线信息本地环路，ITU国际标准）等多项国家标准和国际标准。北京信威曾荣获国家科技进步一等奖、中国专利金奖、信息产业重大技术发明奖等多项殊荣，是国家首批创新型试点企业之一，是“无线移动通信国家重点实验室”依托单位，得到“新一代宽带无线移动通信网”国家科技重大专项以及国家电子信息产业振兴规划的

5、重点支持。北京信威以“开朗、勤奋、务实、创新”的精神，通过不懈努力，使得中国的无线宽带通信技术走在了世界前列。信威通信产业集团下属主要机构：Major Subsidiaries under Xinwei Telecom Enterprise Group北京信威通信技术股份有限公司Beijing Xinwei Telecom Technology INC.清华信威空天信息网络技术联合研究中心Tsinghua University-Beijing Xinwei Telecom Technology Inc. Joint Research Center for Aerospace Informati

6、on Network Technology重庆信威通信技术有限责任公司Chongqing Xinwei Telecom Technology Co.,LTD.深圳信威通信技术有限公司Shenzhen Xinwei Telecom Technology Co.,LTD.信威柬埔寨电信有限公司Xinwei（Cambodia）Telecom Co.,LTD.北京信威合创国际贸易有限公司Beijing Xinwei Alliance International Trading Co.,LTD.北京瑞平通信技术有限公司Beijing Arrowping Telecom Technology Co.,LT

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8、or Relations | 合作伙伴 人才招聘: 服务热线 400-886-0051 或Email:hr个人求职: Email:club或垂询400-820-5100，800-820-5100未经 同意，不得转载本网站之所有招聘信息及作品无忧工作网版权所有1999-2011Research Highlights Meeting the challenges associated with producing a Just-in-Time solution to building maintenance. Offering a holistic life-cycle approach to b

9、uilding design and maintenance scheduling. Exploring the benefits of 4D, with the 4th dimension being the ability to travel through time, to help with design and maintenance decisions. Providing Integrating building component life-cycle simulation with building information model and visual interface

10、.254Network-on-Chip interconnect for pairing-based cryptographic IP coresOriginal Research ArticleJournal of Systems Architecture, Volume 57, Issue 1, January 2011, Pages 95-108Tom English, Emanuel Popovici, Maurice Keller, W.P. MarnaneClose preview| PDF (2405 K) | Related articles|Related reference

11、 work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractOn-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, co

12、ngestion and scalability problems. In this paper, two case study cryptographic IP cores with demanding interconnect requirements are implemented on 65nm CMOS. Lightweight, custom bus-replacement Networks-on-Chip (NoCs) have been developed for both cores. Results show that eliminating the 251-bit-wid

13、e cross-chip cryptographic buses dramatically improves the quality of physical implementation. The results have applicability to wire-constrained designs in other domains.Article Outline1. Introduction 1.1. Identity-based Encryption1.2. Hardware Architectures for Pairing-based Cryptosystems (PBC)1.3

14、. Bus-replacement NoCs for PBC IP cores2. Related work 2.1. Bus-replacement NoCs2.2. Pairing-based cryptographic IP cores3. Case Study IP cores Architecture and implementation 3.1. CS1 Architecture3.2. CS1 inter-PE communication3.3. CS2 Architecture3.4. CS2 inter-PE communication3.5. Implementation

15、flow4. Bus-replacement NoCs for Case Study IP cores 4.1. CS1 NoC Architecture4.2. CS1 NoC implementation4.3. CS1 NoC results4.4. Reducing circuit-switching NoC overhead4.5. CS1 with point-to-point link interconnect4.6. CS1 point-to-point links results4.7. CS2 NoC specification4.8. CS2 NoC design4.9.

16、 CS2 NoC implementation4.10. CS2 Saturn NoC results5. ConclusionAcknowledgementsReferencesVitae255Joint random access and power control game in ad hoc networks with noncooperative usersOriginal Research ArticleAd Hoc Networks, Volume 9, Issue 2, March 2011, Pages 142-151Chengnian Long, Qun Chi, Xinp

17、ing Guan, Tongwen ChenClose preview| Related articles|Related reference work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractWe consider a distributed joint random access and power control scheme for interference management in wireless ad hoc networks. To deri

18、ve decentralized solutions that do not require any cooperation among the users, we formulate this problem as noncooperative joint random access and power control game, in which each user minimizes its average transmission cost with a given rate constraint. Using supermodular game theory, the existen

19、ce and uniqueness of Nash equilibrium are established. Furthermore, we present an asynchronous distributed algorithm to compute the solution of the game based on myopic best response updates, which converges to Nash equilibrium globally. Finally, a link admission algorithm is carried out to guarante

20、e the reliability of the active users. Performance evaluations via simulations show that the game-theoretical based cross-layer design achieves high performance in terms of energy consumption and network stability.Article Outline1. Introduction2. Related work3. System model and problem formulation 3

21、.1. Random access, power control and link capacity3.2. Joint random access and power control game4. Existence of Nash equilibrium5. Distributed algorithm6. The Feasibility of JRPG7. Simulation results8. Conclusion and future workAcknowledgementsReferencesVitaePurchase$ 27.95256Area and power-efficie

22、nt innovative congestion-aware Network-on-Chip architectureOriginal Research ArticleJournal of Systems Architecture, Volume 57, Issue 1, January 2011, Pages 24-38Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader BagherzadehClose preview| PDF (3878 K) | Related articles|Related reference work article

23、s AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractThis paper proposes a novel Network-on-Chip architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also provides a power-efficient solution for interco

24、nnection network scenarios. Diagonally-linked mesh NoC that uses wormhole packet switching technique implements a high-performance NoC platform to meet both cost and power consumption requirements. The proposed architecture uses an adaptive quasi-minimal routing algorithm so that it can improve aver

25、age latency and saturation traffic load owing to its flexibility and adaptiveness. Based on these features, a congestion-aware routing algorithm is proposed to balance traffic load so as to alleviate congestion caused by high throughput network activities. Simulation results show that saturation loa

26、d is improved dramatically for various traffic patterns. Implementation results also show that employing diagonal links is a more area-efficient method for improving network performance than using large buffers. It is shown that congestion-aware router requires negligible cost overhead but provides

27、better throughput. Finally, simulation results also reveal that power consumption in the proposed architecture outperforms traditional mesh networks.Article Outline1. Introduction2. Background and prior work 2.1. Noc architecture 2.1.1. Switching technique2.1.2. Topology development2.1.3. Routing po

28、licy2.2. NePA system platform2.3. Prior work3. DMesh architecture 3.1. System platform description3.2. Packet format3.3. Routing algorithm3.4. Congestion-aware router architecrture 3.4.1. Dynamic input port arbitration3.4.2. Adaptive path selection3.4.3. CA router variants 3.4.3.1. CA_IN3.4.3.2. CA_

29、OUT3.4.3.3. CA_HYBRID4. Evaluation 4.1. Experimental setup4.2. Performance evaluation 4.2.1. DMesh performance evaluation4.2.2. Congestion-aware scheme evaluation4.3. Implementation cost evaluation4.4. Power consumption evaluation5. Conclusion and future workReferencesVitae257An architecture model t

30、o support cooperative design for mechatronic products: A control design caseOriginal Research ArticleMechatronics, Volume 21, Issue 3, April 2011, Pages 534-547A.A. Alvarez Cabrera, K. Woestenenk, T. TomiyamaClose preview| Related articles|Related reference work articles AbstractAbstract | Figures/TablesFigures/Tables | ReferencesReferences AbstractEfficient integration of systems in the mec