JH5001二次开发实验指导书老师供综合设计参考.docx

1、JH5001二次开发实验指导书老师供综合设计参考JH5001二次开发参考程序（以下所有程序均调试通过，可作为编程参考）二OO三年一月课程设计一、 可变分频器的实验TITLE Counter;SUBDESIGN Counter( %pcm input% FSX_PCM,BCLKT,DT_PCM :INPUT; %m sequence% m_Sequence :INPUT; %SW input% SW7.0 :INPUT; %control mode% Error_SEL1.0 :INPUT; %MUX output% MUX_DT :OUTPUT; MUX_CLK :INPUT; Error_i

2、nd :OUTPUT; %Test m sequence% m_SEL1.0 :INPUT; m_test :OUTPUT; Frame_Ind :OUTPUT; )VARIABLE Main_CLK :LCELL; Counter7.0 :DFF; Mode1.0 :LCELL; Counter_Out :LCELL; %students pust defined variables at here% Counter_Reset :LCELL; Counter_Out_Buff :DFF;BEGIN Main_CLK=MUX_CLK; Mode=M_SEL;%INPUT: Main_CLK:

3、 input 256KHz clock Mode1.0: Control counter mode Counter_Out: Counter outputfunction: if Mode=0: Counter_Out=Main_CLK/213; if Mode=1: Counter_Out=Main_CLK/187; if Mode=2: Counter_Out=Main_CLK/156; if Mode=3: Counter_Out=Main_CLK/15;% -students put his program inhere CASE Mode IS WHEN 0 = Counter_Re

4、set=(Counter=212); WHEN 1 = Counter_Reset=(Counter=186); WHEN 2 = Counter_Reset=(Counter=155); WHEN 3 = Counter_Reset=(Counter=14); END CASE; Counter.clk=Main_CLK; CASE (Counter_Reset) IS WHEN 0 = Counter.d=Counter+1; WHEN 1 = Counter.d=0; END CASE; Counter_Out_Buff.clk=!Main_CLK; CASE Mode IS WHEN

5、0 = Counter_Out_Buff.d=(Counter Counter_Out_Buff.d=(Counter Counter_Out_Buff.d=(Counter Counter_Out_Buff.d=(Counter Delay_m6.d=Delay_m5 $ Delay_m4 $ All_Zero; WHEN 1 = Delay_m6.d=Delay_m4 $ Delay_m3 $ All_Zero; WHEN 2 = Delay_m6.d=Delay_m2 $ Delay_m1 $ All_Zero; WHEN 3 = Delay_m6.d=Delay_m1 $ Delay_

6、m0 $ All_Zero; END CASE; m_out=Delay_m6; -fellowing program cant be rewriteable m_test=m_Out; -not used pin MUX_DT=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,SW7.0,Error_SEL1.0,MUX_CLK)=0; (Error_ind,Frame_Ind)=0; END;课程设计三、 噪声信号的产生TITLE noise generating;SUBDESIGN Noise( %MUX input% MUX_DR,MUX_CLKR :INPUT; %P

7、CM output% DR_PCM :OUTPUT; FSR,BCLKR :INPUT; %m output% DR_m :OUTPUT; Frame_Ind :OUTPUT; %SW output% SW_Out7.0 :OUTPUT;)VARIABLE Delay_m24.0 :DFF; PCM_Count3.0,DR_PCM :DFF;BEGIN % input: FSR: PCM frame indication BCLKR: PCM data input clock Output: DR_PCM: noise PCM code function: this program outpu

8、t noise to PCM decoder % %m sequence generating% Delay_m.clk=FSR; Delay_m23.0.d=Delay_m24.1;-200000011 Delay_m24.d=Delay_m3 $ Delay_m0 $ (Delay_m=0); %PCM output% PCM_Count.d=PCM_Count+1; PCM_Count.clk=BCLKR & FSR; PCM_COunt.clrn=FSR; DR_PCM.clk=!BCLKR; CASE PCM_Count IS WHEN 0 = DR_PCM.d=Delay_m0;

9、WHEN 1 = DR_PCM.d=Delay_m1; WHEN 2 = DR_PCM.d=Delay_m2; WHEN 3 = DR_PCM.d=Delay_m3; WHEN 4 = DR_PCM.d=Delay_m4; WHEN 5 = DR_PCM.d=Delay_m5; WHEN 6 = DR_PCM.d=Delay_m6; WHEN 7 = DR_PCM.d=Delay_m7; END CASE; %fellowing program cant be writeable% (DR_m,Frame_Ind)=(MUX_DR,MUX_CLKR)=0); SW_Out7.0=Delay_m

10、7.0;END;课程设计四、 复接实验TITLE FRAME;%=MUXplex data defining=%CONSTANT UW=B11100100;CONSTANT DataA=h11;CONSTANT DataB=h22;SUBDESIGN Frame( %pcm input% FSX_PCM,BCLKT,DT_PCM :INPUT; %m sequence% m_Sequence :INPUT; %SW input% SW7.0 :INPUT; %control mode% Error_SEL1.0 :INPUT; %MUX output% MUX_DT :OUTPUT; MUX_

11、CLK :INPUT; Error_ind :OUTPUT; %Test m sequence% m_SEL1.0 :INPUT; m_test :OUTPUT; Frame_Ind :OUTPUT; )VARIABLE %students define variable in here% Count4.0,load,Send_buff7.0 :DFF; MUX_DT :DFF; Send_bit :LCELL;BEGIN%INPUT: MUX_CLK: input multiplex 256KHz clock SW7.0: multiplex data 1 - 8 bit switch in

12、formation DataA: multiplex data A which is define as constant DataB: multiplex data B which is define as constant UW: multiplex data B which is define as constantoutput: MUX_DT: multiplex data output Frame_Int: Frame indicationfunction: ultiplex DataA, DataB,SW,UW is combined as one output data stre

13、am% %=students program put here=% %32 byte counter for per frame is 32 bit% Count.clk=MUX_CLK; Count.d=Count+1; Frame_Ind=Count4; %load generating% load.d=(Count=31) # (Count=7) # (Count=15) # (Count=23); load.clk=!MUX_CLK; %load data% Send_buff.clk=load; CASE (Count4.3) IS WHEN 0 = Send_Buff.d=UW;

14、WHEN 1 = Send_Buff.d=DataA; WHEN 2 = Send_Buff.d=DataB; WHEN 3 = Send_Buff.d=SW; END CASE; %parallel to serial% CASE Count2.0 IS WHEN 0 = Send_bit=Send_buff7; WHEN 1 = Send_bit=Send_buff6; WHEN 2 = Send_bit=Send_buff5; WHEN 3 = Send_bit=Send_buff4; WHEN 4 = Send_bit=Send_buff3; WHEN 5 = Send_bit=Sen

15、d_buff2; WHEN 6 = Send_bit=Send_buff1; WHEN 7 = Send_bit=Send_buff0; END CASE; MUX_DT.d=Send_bit; MUX_DT.clk=!MUX_CLK; %fellowing cant be rewriteable% Error_ind=(FSX_PCM,BCLKT,DT_PCM,m_Sequence,Error_SEL1.0,m_SEL)=0; m_test=GND;END;课程设计五、 帧同步实验TITLE deframe;%=UW define=%CONSTANT UW=B11100100;SUBDESI

16、GN DeFrame( %MUX input% MUX_DR,MUX_CLKR :INPUT; %PCM output% DR_PCM :OUTPUT; FSR,BCLKR :INPUT; %m output% DR_m :OUTPUT; Frame_Ind :OUTPUT; %SW output% SW_Out7.0 :OUTPUT;)VARIABLE %=student variable define=% -serial to parallel stop_Buff7.0 :DFF; -load word Line_Count4.0 :DFF; Load_UW,UW_Buff7.0 :DFF

17、; Load_DataA,DataA_Buff7.0 :DFF; load_DataB,DataB_Buff7.0 :DFF; load_SW,SW_Buff7.0 :DFF; %detect period counter% Period_Count9.0 :DFF; %synchronous% NO_SYN,Reset :DFF; Delay_NO_SYN2.0 :DFF; Loss_one_Clock,Hold_Count :LCELL; Error_Word_Count4.0 :DFF; Frame_ind :DFF; BEGIN%INPUT: MUX_CLK: input multip

18、lex 256KHz clock MUX_DR: multiplex dataoutput: DataA: multiplex data A which is define as constant DataB: multiplex data B which is define as constant SW: multiplex SW UW: multiplex data UW Frame_Ind: receiver frame indicationfunction: demultiplex DataA, DataB,SW,UW is extracted from input data stre

19、am% %=students program put here=% %Clock for m sequence% Frame_ind.d=(Line_Count=0); Frame_ind.clk=!MUX_CLKR; %serial to parallel% stop_Buff7.1.d=stop_Buff6.0; stop_Buff0.d=MUX_DR; stop_Buff.clk=MUX_CLKR; %load word% Line_Count.d=Line_Count+1; Line_Count.clk=(MUX_CLKR & !Loss_one_Clock); -load UW wo

20、rd load_UW.d=(Line_Count=7); load_UW.clk=!MUX_CLKR; UW_buff.d=stop_Buff; UW_buff.clk=load_UW; -load DataA load_DataA.d=(Line_Count=15); load_DataA.clk=!MUX_CLKR; DataA_buff.d=stop_Buff; DataA_buff.clk=load_DataA; -load DataB load_DataB.d=(Line_Count=23); load_DataB.clk=!MUX_CLKR; DataB_buff.d=stop_B

21、uff; DataB_buff.clk=load_DataB; -load SW load_SW.d=(Line_Count=31); load_SW.clk=!MUX_CLKR; SW_buff.d=stop_Buff; SW_buff.clk=load_SW; SW_Out=SW_buff; %period counter% Period_Count.d=Period_Count+1;-512 frame Period_Count.clk=Load_UW; %synchronous% NO_SYN.d=(Error_Word_Count30); NO_SYN.clk=load_UW; Re

22、set.d=(period_Count=1); Reset.clk=Load_UW; %loss one clock generating% Delay_NO_SYN2.0.clk=!MUX_CLKR; Delay_NO_SYN2.1.d=Delay_NO_SYN1.0; Delay_NO_SYN0.d=NO_SYN; Loss_one_Clock=(Delay_NO_SYN2 $ Delay_NO_SYN1) & Delay_NO_SYN1; %eror word counter% Error_Word_Count.clrn=!Reset; Error_Word_Count.clk=!loa

23、d_UW; Hold_Count=(Error_Word_Count=31); CASE (Hold_Count,(UW_Buff=UW) IS WHEN 0 = Error_Word_Count.d=Error_Word_Count+1; WHEN OTHERS = Error_Word_Count.d=Error_Word_Count; END CASE; %fellowing program cant be change% (DR_PCM,DR_m)=(FSR,BCLKR)=0) $ (DataA_Buff=0) $ (DataB_Buff=0); END;课程设计六、 扰码实验TITLE Scrambler