VHDL计数器程序.docx

1、VHDL计数器程序VHDL-计数器程序十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGI

2、NPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1110) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF

3、(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_

4、edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_ed

5、ge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fourteencout;ARCHITECTURE counter OF fourteenc

6、out ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1101) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS

7、;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1

8、;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-

9、if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto

10、0);END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1100) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_

11、int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clo

12、ck = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT U

13、NTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable :

14、IN std_logic; count : OUT std_logic_vector(3 downto 0);END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1011) THENcount_int=0000;ELSEco

15、unt_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVEN

16、T AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WA

17、IT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.al

18、l;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 TH

19、ENIF(count_int=1010) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait u

20、ntil (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT riseedge

21、clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;十计数器library ieee;use ieee.std_

22、logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END count;ARCHITECTURE counter OF count ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = 1 THENco

23、unt_int 0);ELSIF enable = 1 THENIF(count_int=1001) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (r

24、eset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT AND clock = 1);- q=q 1;-end if;-count=q;- WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-clockevent and clock=1;-count = 0;-WAIT UNTIL (clockEVENT

25、AND clock = 1);-WAIT riseedge clock = 1;-if (clockevent and clock=1) then-WAIT UNTIL rising_edge(clock);-count = 1;-WAIT UNTIL (clockEVENT AND clock = 1);-WAIT UNTIL clock = 1;-if (clockevent and clock=1)then-WAIT UNTIL rising_edge(clock);-count = 2;-end if;-end if;-end if;- END PROCESS;END counter;

26、九计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNT

27、IL rising_edge(clk);IF reset = 1 THENcount_int 0);ELSIF enable = 1 THENIF(count_int=1000) THENcount_int=0000;ELSEcount_int = count_int 1;-ELSE- NULL ;-IF (count_int=1001) THEN-count_int=0000;END IF;END IF;END PROCESS;count = count_int;- IF (reset=0) then-q=0000;-ELSIF(clkevent and clk=1) THEN-q=q 1;-IF (q=1001) then-q=0000;-END IF;-IF (reset=1)THEN-q=00;-ELSIF-wait until (clkevent and clk=1);-WAIT UNTIL (clkEVENT AND clk = 1);-WAIT UNTIL (clockEVENT