数码管计时 verilog.docx

1、数码管计时 verilog数码管计时 （verilog）学习笔记代码分析：timescale 1ns / 1ps/module seg7( clk,rst_n, ds_stcp,ds_shcp,ds_data );input clk; /25M输入时钟信号input rst_n; /复位信号输入，低有效output ds_stcp; /74HC595的并行时钟输入，上升沿将当前串行输入数据并行输出output ds_shcp; /74HC595的串行时钟输入，上升沿锁存当前串行输入数据output ds_data; /74HC595的串行数据输入/数码管显示 0F 对应段选输出paramete

2、r SEG_NUM0 = 8h3f,/c0, SEG_NUM1 = 8h06,/f9, SEG_NUM2 = 8h5b,/a4, SEG_NUM3 = 8h4f,/b0, SEG_NUM4 = 8h66,/99, SEG_NUM5 = 8h6d,/92, SEG_NUM6 = 8h7d,/82, SEG_NUM7 = 8h07,/F8, SEG_NUM8 = 8h7f,/80, SEG_NUM9 = 8h6f,/90, SEG_NUMA = 8h77,/88, SEG_NUMB = 8h7c,/83, SEG_NUMC = 8h39,/c6, SEG_NUMD = 8h5e,/a1, SEG_

3、NUME = 8h79,/86, SEG_NUMF = 8h71;/8e;/数码管位选 03 对应输出parameter SEG_WE0 = 4b1110, SEG_WE1 = 4b1101, SEG_WE2 = 4b1011, SEG_WE3 = 4b0111;/递增数据产生单元reg24:0 cnt_1s; /1s计数器，0-24999999（时钟频率25MHz）reg15:0 dis_data; /数码管显示数据，16位 /1s定时计数always (posedge clk or negedge rst_n) if(!rst_n) cnt_1s = 25d0; else if(cnt_1

4、s = 25d24_999_999) cnt_1s = 25d0; else cnt_1s = cnt_1s+1b1;wire done_1s = (cnt_1s = 25d24_999_999); /1s定时到标志位，高有效一个时钟周期 /显示数据每秒递增always (posedge clk or negedge rst_n) if(!rst_n) dis_data = 16d0; else if(done_1s) dis_data = dis_data+1b1;/-/分时显示数据控制单元reg7:0 seg_num; /当前显示数据reg7:0 seg_duan; /7段数码管段选信号（

5、包括小数点为8段）reg3:0 seg_wei; /7段数码管位选信号reg7:0 cnt_4; /分时计数器，每个clk自加“1”always (posedge clk or negedge rst_n) if(!rst_n) cnt_4 = 8d0; else cnt_4 = cnt_4+1b1;/显示数据，1s内seg_num不变，直到dis_data变化此信号才发生变化always (posedge clk or negedge rst_n) if(!rst_n) seg_num = 8h00; else case(cnt_47:6) 2b00: seg_num = dis_data3

6、:0; /00h3fh 2b01: seg_num = dis_data7:4; /40h7fh 2b10: seg_num = dis_data11:8; /80hbfh 2b11: seg_num = dis_data15:12; /c0hffh default: seg_num = 8h00; endcase/段选数据译码，由于seg_num在1s内保持不变，故此信号1s内保持不变always (posedge clk or negedge rst_n) if(!rst_n) seg_duan = 8h00; else case(seg_num) 4h0: seg_duan = SEG_

7、NUM0; 4h1: seg_duan = SEG_NUM1; 4h2: seg_duan = SEG_NUM2; 4h3: seg_duan = SEG_NUM3; 4h4: seg_duan = SEG_NUM4; 4h5: seg_duan = SEG_NUM5; 4h6: seg_duan = SEG_NUM6; 4h7: seg_duan = SEG_NUM7; 4h8: seg_duan = SEG_NUM8; 4h9: seg_duan = SEG_NUM9; 4ha: seg_duan = SEG_NUMA; 4hb: seg_duan = SEG_NUMB; 4hc: seg

8、_duan = SEG_NUMC; 4hd: seg_duan = SEG_NUMD; 4he: seg_duan = SEG_NUME; 4hf: seg_duan = SEG_NUMF; default: ; endcase/位选译码，2的8次方时间分成4段，每段时间内选通一个7段led管always （cnt_47:6） case(cnt_47:6) 2b00: seg_wei = SEG_WE0; 2b01: seg_wei = SEG_WE1; 2b10: seg_wei = SEG_WE2; 2b11: seg_wei = SEG_WE3; default: seg_wei = 4

9、b1111; endcase/-/74HC95驱动译码 reg ds_stcpr; /74HC595的并行时钟输入，上升沿将当前串行输入数据并行输出reg ds_shcpr; /74HC595的串行时钟输入，上升沿锁存当前串行输入数据reg ds_datar; /74HC595的串行数据输入 /串行移位时钟产生，在cnt_4所处区间上时，即每隔20H个clk周期，ds_shcpr每个clk都会翻转一次，而剩下20H个周期保持之前的状态不变，在cnt_4的计时大周期内发生4次always (posedge clk or negedge rst_n) if(!rst_n) ds_shcpr 8h0

10、2 & cnt_4 8h42 & cnt_4 8h82 & cnt_4 8hc2 & cnt_4 = 8he2) ds_shcpr = ds_shcpr; /串行移位数据产生，在cnt_4的0222期间，每个clk都将seg_duan，seg_wei的1位送给ds_datar，在一个cnt_4计时大周期内总共送4次always (posedge clk or negedge rst_n) if(!rst_n) ds_datar = 1b0; else case(cnt_4) 8h02,8h42,8h82,8hc2: ds_datar = seg_duan7; 8h04,8h44,8h84,8h

11、c4: ds_datar = seg_duan6; 8h06,8h46,8h86,8hc6: ds_datar = seg_duan5; 8h08,8h48,8h88,8hc8: ds_datar = seg_duan4; 8h0a,8h4a,8h8a,8hca: ds_datar = seg_duan3; 8h0c,8h4c,8h8c,8hcc: ds_datar = seg_duan2; 8h0e,8h4e,8h8e,8hce: ds_datar = seg_duan1; 8h10,8h50,8h90,8hd0: ds_datar = seg_duan0; 8h1a,8h5a,8h9a,8

12、hda: ds_datar = seg_wei0; 8h1c,8h5c,8h9c,8hdc: ds_datar = seg_wei1; 8h1e,8h5e,8h9e,8hde: ds_datar = seg_wei2; 8h20,8h60,8ha0,8he0: ds_datar = seg_wei3; default: ; endcase/并行移位时钟产生，即在23,63,a3,e3时刻置“1”，而在02,42,82,c2时刻置“0”always (posedge clk or negedge rst_n) if(!rst_n) ds_stcpr = 1b0; else if(cnt_4 =

13、8h02) | (cnt_4 = 8h42) | (cnt_4 = 8h82) | (cnt_4 = 8hc2) ds_stcpr = 1b0; else if(cnt_4 = 8h23) | (cnt_4 = 8h63) | (cnt_4 = 8ha3) | (cnt_4 = 8he3) ds_stcpr = 1b1;wire ds_stcp = ds_stcpr;wire ds_shcp = ds_shcpr;wire ds_data = ds_datar; endmodule-1.74HC595相关2.模块相关信号定义：信号名称方向描述ClkInput时钟信号，25MHzRst_nInp

14、ut复位信号，低有效Ds_stcpOutput74HC595并行时钟输入，上升沿将当前串行输入数据并行输出Ds_shcpOutput74HC595串行时钟输入，上升沿所存当前串行输入数据Da_dataOutput74HC595的串行输入数据2.程序设计相关最开始参数化定义了SEG_NUM0SEG_NUMF，对应7段数码管的显示，再定义了SEG_WE0SEG_WE3，对应数码管的位选时钟为25MHz，用cnt_1s完成1s计时，1s计时到了，使done_1s信号有效，并使dis_data每秒“+1”之后的代码参考下面这张图来说明Cnt_4每个clk周期计数，其总的计数周期可以分为4段时间，分时扫描显示数据和位选信号。其中seg_num，seg_duan信号在1s时间内不变。至于ds_shcp，ds_data，ds_stcp信号的产生就如下图所示具体的时序就参考特权前辈给的资料里面的对74HC595芯片的资料描述。