数电课程设计交通灯控制逻辑电路设计.docx

1、数电课程设计交通灯控制逻辑电路设计数电课程设计-交通灯控制逻辑电路设计江苏科技大学电子信息学院数字电子技术实验课 程 设 计 报 告指导老师 : 李绍鹏学 院: 电子信息学院班 级: 11403022学生（学号）: 孙磊（1140302219）课题一 数字电子钟课题二 交通灯控制逻辑电路设计（注：由于Quartusii 9.0不支持中文输入，但支持中文复制，所以以下代码文字说明均为后期制作）课题一 数字电子钟任务：用文本法设计一个能显示时、分、秒的数字电子钟要求：1.设计由20mhz有源晶振电路产生标准信号的单元电路； 2.时为0023六十进制计数器，分、秒为0059六十进制计数器； 3.能够

2、显示出时、分、秒； 4.具有清零，调节分钟的功能； 5.模拟钟摆功能； 6.具有整点报时功能，整点报时的同时声响电路发出叫声； 7.对时、分、秒单元电路进行仿真并记录。本文利用Verilog HDL语言自顶向下的设计方法设计多功能数字钟，并通过仿真和下载，实现其基本功能。1顶层文件 module top(CLK,SET,EN,RE, /CLK=20M HZ SET调节分钟LED_5,OUT,QH1,QH0,QM1,QM0,QS1,QS0); input CLK,SET,RE,EN; output OUT; /OUT报时 output 3:0 QH1,QH0,QM1,QM0,QS1,QS0; o

3、utput 4:0 LED_5; wire clk1khz,clk250hz,clk1hz,m1,b2,b3,b4; wire 5:0 s1,m2,h3;/-分频- Div u1(CLK,EN,RE,14d6384,clk1khz); Div u2(clk1khz,EN,RE,14d16382,clk250hz); Div u3(clk1khz,EN,RE,14d15884,clk1hz); /-秒s1计数 ,产生分进位m1- counter u4(clk1hz,EN,RE,6d59,m1,s1); BCDturn u5(s1,QS1,QS0); /-分m2计数，产生时进位b3- counte

4、r u6(b2,EN,RE,6d59,b3,m2); BCDturn u7(m2,QM1,QM0); /-时h3计数，产生进位b4- counter u8(b3,EN,RE,6d23,b4,h3); BCDturn u9(h3,QH1,QH0); /-模拟钟摆- led_ u10 (CLK,LED_5); /-整点报时- baoshi u11(QM1,QM0,QS1,QS0,OUT);/-b2调节分钟- assign b2=SET?SET:m1; endmodule2分频模块module Div(CLK,EN,RE,d,Q); /给d赋初始值 input CLK,EN,RE; input 13

5、:0 d; output Q; reg FULL,Q; reg 13:0 c; always(posedge CLK ) begin if(RE) begin c=d; FULL=0; end else if(EN) begin if(c=141b1) begin c=d; FULL=1; end else begin c=c+1; FULL=0; end end end always(posedge FULL) /得到占空比50%的分频信号 begin Q=Q; endendmodule3计数模块module counter(CLK,EN,RE,C,FULL,Q); /EN=1时进行计数，R

6、E=1时清零 input CLK,EN,RE; /C表示N进制，Q为计数结果 input 5:0 C; output 5:0Q; output FULL; reg 5:0Q; reg FULL; always(posedge CLK) begin if(RE) begin Q=0; FULL=0; end else if(EN) begin if(Q=C) begin Q=0; FULL=1; end else begin Q=Q+1; FULL=0; end end end endmodule4BCD译码模块/由于计数使用的二进制，在输出时便需要进行译码，转换成大众所熟悉的十进制表示modu

7、le BCDturn(indec,qh,ql); input 5:0 indec; output 3:0 qh,ql; reg 3:0 qh,ql; always(indec) begin case(indec) 6d0:begin qh3:0=b0000;ql3:0=b0000;end 6d1:begin qh3:0=b0000;ql3:0=b0001;end 6d2:begin qh3:0=b0000;ql3:0=b0010;end 6d3:begin qh3:0=b0000;ql3:0=b0011;end 6d4:begin qh3:0=b0000;ql3:0=b0100;end 6d5

8、:begin qh3:0=b0000;ql3:0=b0101;end 6d6:begin qh3:0=b0000;ql3:0=b0110;end 6d7:begin qh3:0=b0000;ql3:0=b0111;end 6d8:begin qh3:0=b0000;ql3:0=b1000;end 6d9:begin qh3:0=b0000;ql3:0=b1001;end 6d10:begin qh3:0=b0001;ql3:0=b0000;end 6d11:begin qh3:0=b0001;ql3:0=b0001;end 6d12:begin qh3:0=b0001;ql3:0=b0010;

9、end 6d13:begin qh3:0=b0001;ql3:0=b0011;end 6d14:begin qh3:0=b0001;ql3:0=b0100;end 6d15:begin qh3:0=b0001;ql3:0=b0101;end 6d16:begin qh3:0=b0001;ql3:0=b0110;end 6d17:begin qh3:0=b0001;ql3:0=b0111;end 6d18:begin qh3:0=b0001;ql3:0=b1000;end 6d19:begin qh3:0=b0001;ql3:0=b1001;end 6d20:begin qh3:0=b0010;

10、ql3:0=b0000;end 6d21:begin qh3:0=b0010;ql3:0=b0001;end 6d22:begin qh3:0=b0010;ql3:0=b0010;end 6d23:begin qh3:0=b0010;ql3:0=b0011;end 6d24:begin qh3:0=b0010;ql3:0=b0100;end 6d25:begin qh3:0=b0010;ql3:0=b0101;end 6d26:begin qh3:0=b0010;ql3:0=b0110;end 6d27:begin qh3:0=b0010;ql3:0=b0111;end 6d28:begin

11、qh3:0=b0010;ql3:0=b1000;end 6d29:begin qh3:0=b0010;ql3:0=b1001;end 6d30:begin qh3:0=b0011;ql3:0=b0000;end 6d31:begin qh3:0=b0011;ql3:0=b0001;end 6d32:begin qh3:0=b0011;ql3:0=b0010;end 6d33:begin qh3:0=b0011;ql3:0=b0011;end 6d34:begin qh3:0=b0011;ql3:0=b0100;end 6d35:begin qh3:0=b0011;ql3:0=b0101;end

12、 6d36:begin qh3:0=b0011;ql3:0=b0110;end 6d37:begin qh3:0=b0011;ql3:0=b0111;end 6d38:begin qh3:0=b0011;ql3:0=b1000;end 6d39:begin qh3:0=b0011;ql3:0=b1001;end 6d40:begin qh3:0=b0100;ql3:0=b0000;end 6d41:begin qh3:0=b0100;ql3:0=b0001;end 6d42:begin qh3:0=b0100;ql3:0=b0010;end 6d43:begin qh3:0=b0100;ql3

13、:0=b0011;end 6d44:begin qh3:0=b0100;ql3:0=b0100;end 6d45:begin qh3:0=b0100;ql3:0=b0101;end 6d46:begin qh3:0=b0100;ql3:0=b0110;end 6d47:begin qh3:0=b0100;ql3:0=b0111;end 6d48:begin qh3:0=b0100;ql3:0=b1000;end 6d49:begin qh3:0=b0100;ql3:0=b1001;end 6d50:begin qh3:0=b0101;ql3:0=b0000;end 6d51:begin qh3

14、:0=b0101;ql3:0=b0001;end 6d52:begin qh3:0=b0101;ql3:0=b0010;end 6d53:begin qh3:0=b0101;ql3:0=b0011;end 6d54:begin qh3:0=b0101;ql3:0=b0100;end 6d55:begin qh3:0=b0101;ql3:0=b0101;end 6d56:begin qh3:0=b0101;ql3:0=b0110;end 6d57:begin qh3:0=b0101;ql3:0=b0111;end 6d58:begin qh3:0=b0101;ql3:0=b1000;end 6d

15、59:begin qh3:0=b0101;ql3:0=b1001;end default:begin qh3:0=bx;ql3:0=bx;end endcase endEndmodule5模拟钟摆模块/该模块对20mhz的clk进行的分频，所得到的8hz（clk_8hz）用作5个LED的时钟脉冲module led_(clk,ledout); input clk; output4:0ledout; reg4:0ledout; reg12:0count0; reg clk_2khz,clk_8hz; reg6:0count4; reg2:0cnt1;always(posedge clk) beg

16、in if(count0=d5000) /5000 begin clk_2khz=clk_2khz; count0=0; end else begin count0=count0+1; end endalways(posedge clk_2khz) begin if(count4=d125) /125 begin clk_8hz=clk_8hz; count4=0; end else begin count4=count4+1; end endalways(posedge clk_8hz) begin if(cnt1=d7) begin cnt1=d0; end else begin cnt1

17、=cnt1+1; end endalways(cnt1) begin case(cnt1) 3d0:ledout4:0=5b10000; 3d1:ledout4:0=5b01000; 3d2:ledout4:0=5b00100; 3d3:ledout4:0=5b00010; 3d4:ledout4:0=5b00001; 3d5:ledout4:0=5b00010; 3d6:ledout4:0=5b00100; 3d7:ledout4:0=5b01000; endcase endendmodule6整点报时模块/该模块在49:52,49:54,49:56,49:5800:00这6个秒段产生高电平

18、，用作报时module baoshi(qmh,qml,qsh,qsl,OUT); input3:0 qmh,qml,qsh,qsl; output OUT; reg OUT;always( qmh or qml or qsh or qsl) begin if(qmh=4d5&qml=4d9&qsh=4d5&qsl=4d2) OUT=1; else if(qmh=4d5&qml=4d9&qsh=4d5&qsl=4d4) OUT=1; else if(qmh=4d5&qml=4d9&qsh=4d5&qsl=4d6) OUT=1; else if(qmh=4d5&qml=4d9&qsh=4d5&qs

19、l=4d8) OUT=1; else if(qmh=4d5&qml=4d9&qsh=4d5&qsl=4d9) OUT=1; else if(qmh=4d0&qml=4d0&qsh=4d0&qsl=4d0) OUT=1; else OUT=0; endendmodule逻辑功能仿真结果：调节分钟：模拟钟摆：通过以上仿真，在实验板上进行测试，管脚锁定：实验最终测试运行良好，并通过验收。课题二 交通灯控制逻辑电路设计任务：用CPLD设计路口交通灯控制器要求：1.满足如下时序要求：南北方向红灯亮，东西方向绿灯亮；南北方向绿灯亮，东西方 向红灯亮； 2.每一方向的红（绿）黄灯总共维持30秒； 3.十字路

20、口要有时间显示，具体为：当某一方向绿灯亮时，置显示器为30秒，然后 以每秒减一计数方式工作，直至减到数为4秒时，红绿灯熄灭，黄灯开始间隙闪耀 4秒，减到零时，红绿灯交换，一次工作循环结束，进入下一步另一方向的工作循 环； 4.红绿黄灯均采用发光二极管； 5.设计由晶振电路产生1Hz标准秒信号的单元电路； 6.要求对整体电路进行仿真，观察并记录下仿真波形； 7.东西方向或南北方向的绿灯亮变为红灯亮，中间需插入黄灯闪耀4秒过渡，而从红灯亮变为绿灯亮，不需要黄灯过渡，直接由红灯变为绿灯。文本文件：module traffic(qh,ql,clk,clr,enmergy,ra,ya,ga,rb,yb,

21、gb); output ra,ya,ga,rb,yb,gb; /东西方向红（ra）黄（ya）绿（ga）；南北方向红（rb）黄（yb） output3:0 qh,ql; /绿（gb） input clk,clr,enmergy; /enmergy 紧急信号，该信号有效时，所有交通灯皆显红灯 reg1:0state,next_state; parameter state0=2b00,state1=2b01,state2=2b10,state3=2b11; reg clk_1khz,clk_1hz,clk_2hz; reg3:0 qh,ql; reg r1,r2,g1,g2,y1,y2; reg r

22、a,ya,ga,rb,yb,gb; reg13:0count1; reg8:0count2,count3; reg a; reg4:0timer; always(posedge clk) begin if(count1=14d10000) /10000 begin clk_1khz=clk_1khz; count1=0; end else begin count1=count1+1; end endalways(posedge clk_1khz)begin if(count2=9d500) /500 begin clk_1hz=clk_1hz; count2=0; end else begin

23、 count2=count2+1; end if(count3=d250) /250 begin clk_2hz=clk_2hz; count3=0; end else begin count3=count3+1; endendalways(posedge clk_1hz)beginif(clr) begin r1=0;y1=0;g1=0; r2=0;y2=0;g2=0; endelse begin state=next_state; case(state) state0:begin if(!enmergy) begin if(!a) begin timer=5d30; a=1; r1=0;y

24、1=0;g1=1; r2=1;y2=0;g2=0; end else begin if(timer=1) begin next_state=state1; a=0; timer=0; end else timer=timer-1; end end end state1:begin if(!enmergy) begin if(!a) begin timer=5d4; a=1; r1=0;y1=1;g1=0; r2=1;y2=0;g2=0; end else begin if(timer=1) begin next_state=state2; a=0; timer=0; end else timer=timer-1; end end end state2:begin if(!enmergy) begin if(!a) begin timer=5d25; a=1; r1=1;y1=0;g1=0; r2=0;y2=0;g2=1; end else begin if(t