DE2 实验练习解答lab4 countersverilogdigital logic.docx

1、DE2 实验练习解答lab4 countersverilogdigital logic本练习的目的是使用计数器。Part I 用T触发器实现16-bit的计数器参照图 1所示的4-bit的同步计数器，实现一个16-bit 的计数器。代码 1/top-level file 2module part1(KEY0,SW,HEX3,HEX2,HEX1,HEX0); 3input KEY0; /时钟脉冲 4input 1:0SW; /使能&复位 5output 6:0HEX3,HEX2,HEX1,HEX0; /输出显示 6wire 15:0q; /16-bit计数输出 7 8 counter_16(SW

2、1,KEY0,SW0,q); 910 seg7_lut H0(q3:0,HEX0);11 seg7_lut H1(q7:4,HEX1);12 seg7_lut H2(q11:8,HEX2);13 seg7_lut H3(q15:12,HEX3);1415endmodule 1/由T触发器构建的16-bit计数器 2module counter_16(en,clk,clr,Q); 3inputen,clk,clr; 4wire 15:0q; 5output 15:0Q; 6t_ff u0(en,clk,clr,q0); 7t_ff u1(en&q0,clk,clr,q1); 8t_ff u2(e

3、n&q0&q1,clk,clr,q2); 9t_ff u3(en&q0&q1&q2,clk,clr,q3);10t_ff u4(en&q0&q1&q2&q3,clk,clr,q4);11t_ff u5(en&q0&q1&q2&q3&q4,clk,clr,q5);12t_ff u6(en&q0&q1&q2&q3&q4&q5,clk,clr,q6);13t_ff u7(en&q0&q1&q2&q3&q4&q5&q6,clk,clr,q7);14t_ff u8(en&q0&q1&q2&q3&q4&q5&q6&q7,clk,clr,q8);15t_ff u9(en&q0&q1&q2&q3&q4&q5&

4、q6&q7&q8,16clk,clr,q9);17t_ff u10(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9,18clk,clr,q10); 19t_ff u11(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10,20clk,clr,q11); 21t_ff u12(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11,22clk,clr,q12); 23t_ff u13(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11&q12,24clk,clr,q13); 25t_ff u14(en

5、&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11&q12&q13,26clk,clr,q14); 27t_ff u15(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11&q12&q13&q14,28clk,clr,q15); 2930assign Q=q; 3132endmodule 1/T flip flop 2modulet_ff(t,clk,rst_n,q); 3inputt,clk,rst_n; 4outputreg q; 5 6always (posedgeclk) 7begin 8if(!rst_n) 9 q=0;10el

6、se11begin12if(t=1b1)13 q=q;14else15 q=q;16end17end1819endmodule图值图占用的数量Part用赋值语句实现-计数器代码 1/counter-16bit 2module part2(clk,rst_n,q); 3inputclk,rst_n; 4outputreg 15:0q; 5 6always (posedgeclk) 7begin 8if(!rst_n) 9 q=1b0;10else11begin12if(q=65535)13 q=0;14else15 q=q+1;16end17end1819endmodule图-计数器的视图图值图

7、-计数器占用的Part用实现-计数器代码1/Top-level file2modulecounter_lpm(en,clk,clr,q);3inputen,clk,clr;4output 15:0q;56megcounter counter_16bit(.clock(clk),.cnt_en(en),.sclr(clr),7 .q(q)8 );9endmodule 1/ synopsystranslate_off 2timescale 1ps / 1ps 3/ synopsystranslate_on 4modulemegcounter ( 5 clock, 6cnt_en, 7sclr, 8

8、 q); 910input clock;11inputcnt_en;12inputsclr;13output 15:0 q;1415wire 15:0 sub_wire0;16wire 15:0 q = sub_wire015:0;1718lpm_counterlpm_counter_component (19 .sclr (sclr),20 .clock (clock),21 .cnt_en (cnt_en),22 .q (sub_wire0),23 .aclr (1b0),24 .aload (1b0),25 .aset (1b0),26 .cin (1b1),27 .clk_en (1b

9、1),28 .cout (),29 .data (161b0),30 .eq (),31 .sload (1b0),32 .sset (1b0),33 .updown (1b1);34defparam35lpm_counter_component.lpm_direction = UP,36lpm_counter_component.lpm_port_updown = PORT_UNUSED,37lpm_counter_component.lpm_type = LPM_COUNTER,38lpm_counter_component.lpm_width = 16;394041endmodule图用

10、实现-计数器所占用的Part循环显示-在上循环显示-，每秒刷新一次。代码 1/top-level file 2moduleseg_number( 3output 6:0HEX0, 4input CLOCK_50, 5input 0:0KEY 6 ); 7 8wire clk_1hz; 9reg 3:0cnt; 10 11 div u0( 12 .o_clk(clk_1hz), 13 .i_clk(CLOCK_50), 14 .rst_n(KEY) 15 ); 16 17always (posedge clk_1hz ornegedge KEY) 18begin 19if(!KEY) 20cnt

11、=4b0; 21else 22begin 23if(cnt=4d9) 24cnt=4b0; 25else 26cnt=cnt+1b1; 27end 28end 29 30 seg7_lut u1( 31 .oseg(HEX0), 32 .idig(cnt3:0) 33 ); 34endmodule 35 36/divider 37module div( 38outputrego_clk, 39inputrst_n, 40inputi_clk 41 ); 42 43parameter N=50_000_000; 44parameter M=24_999_999; 45 46reg 25:0cnt

12、; 47 48always (posedgei_clkornegedgerst_n) 49begin 50if(!rst_n) 51cnt=26b0; 52else 53begin 54if(cnt=N-1) 55cnt=26b0; 56else 57cnt=cnt+26b1; 58end 59end 60always (posedgei_clkornegedgerst_n) 61begin 62if(!rst_n) 63o_clk=0; 64else 65begin 66if(cnt=M) 67o_clk=1; 68else 69o_clk=0; 70end 71end 72 73endmo

13、dule 74 75/seg7_lut 76module seg7_lut ( 77outputreg 6:0 oseg, 78input 3:0 idig 79); 80always (idig) 81begin 82case (idig) 834h1: oseg = 7b1111001; / -t- 844h2: oseg = 7b0100100; / | | 854h3: oseg = 7b0110000; / ltrt 864h4: oseg = 7b0011001; / | | 874h5: oseg = 7b0010010; / -m- 884h6: oseg = 7b0000010; / | | 894h7: oseg = 7