基于FPEG的SOC设计mips指令系统verilog代码.docx

1、基于FPEG的SOC设计mips指令系统verilog代码/-/基于FPEG的SOC设计/ mips.v/ Model of subset of MIPS processor described in Ch 1/-/ top level design for testingmodule top #(parameter WIDTH = 8, REGBITS = 3)(); reg clk; reg reset; wire memread, memwrite; wire WIDTH-1:0 adr, writedata; wire WIDTH-1:0 memdata; / instantiate

2、devices to be tested mips #(WIDTH,REGBITS) dut(clk, reset, memdata, memread, memwrite, adr, writedata); / external memory for code and data exmemory #(WIDTH) exmem(clk, memwrite, adr, writedata, memdata); / initialize test initial begin reset = 1; # 22; reset = 0; end / generate clock to sequence te

3、sts always begin clk = 1; # 5; clk = 0; # 5; end always(negedge clk) begin if(memwrite) if(adr = 5 & writedata = 7) $display(Simulation completely successful); else $display(Simulation failed); endendmodule/ external memory accessed by MIPSmodule exmemory #(parameter WIDTH = 8) (clk, memwrite, adr,

4、writedata, memdata); input clk; input memwrite; input WIDTH-1:0 adr, writedata; output reg WIDTH-1:0 memdata; reg 31:0 RAM (127:0 215:8 223:16 231:24 2; always (*) case (adr1:0) 2b00: memdata = word31:24; 2b01: memdata = word23:16; 2b10: memdata = word15:8; 2b11: memdata = word7:0; endcaseendmodule/

5、 simplified MIPS processormodule mips #(parameter WIDTH = 8, REGBITS = 3) (input clk, reset, input WIDTH-1:0 memdata, output memread, memwrite, output WIDTH-1:0 adr, writedata); wire 31:0 instr; wire zero, alusrca, memtoreg, iord, pcen, regwrite, regdst; wire 1:0 aluop,pcsource,alusrcb; wire 3:0 irw

6、rite; wire 2:0 alucont; controller cont(clk, reset, instr31:26, zero, memread, memwrite, alusrca, memtoreg, iord, pcen, regwrite, regdst, pcsource, alusrcb, aluop, irwrite); alucontrol ac(aluop, instr5:0, alucont); datapath #(WIDTH, REGBITS) dp(clk, reset, memdata, alusrca, memtoreg, iord, pcen, reg

7、write, regdst, pcsource, alusrcb, irwrite, alucont, zero, instr, adr, writedata);endmodulemodule controller(input clk, reset, input 5:0 op, input zero, output reg memread, memwrite, alusrca, memtoreg, iord, output pcen, output reg regwrite, regdst, output reg 1:0 pcsource, alusrcb, aluop, output reg

8、 3:0 irwrite); parameter FETCH1 = 4b0001; parameter FETCH2 = 4b0010; parameter FETCH3 = 4b0011; parameter FETCH4 = 4b0100; parameter DECODE = 4b0101; parameter MEMADR = 4b0110; parameter LBRD = 4b0111; parameter LBWR = 4b1000; parameter SBWR = 4b1001; parameter RTYPEEX = 4b1010; parameter RTYPEWR =

9、4b1011; parameter BEQEX = 4b1100; parameter JEX = 4b1101; parameter LB = 6b100000; parameter SB = 6b101000; parameter RTYPE = 6b0; parameter BEQ = 6b000100; parameter J = 6b000010; reg 3:0 state, nextstate; reg pcwrite, pcwritecond; / state register always (posedge clk) if(reset) state = FETCH1; els

10、e state = nextstate; / next state logic always (*) begin case(state) FETCH1: nextstate = FETCH2; FETCH2: nextstate = FETCH3; FETCH3: nextstate = FETCH4; FETCH4: nextstate = DECODE; DECODE: case(op) LB: nextstate = MEMADR; SB: nextstate = MEMADR; RTYPE: nextstate = RTYPEEX; BEQ: nextstate = BEQEX; J:

11、 nextstate = JEX; default: nextstate = FETCH1; / should never happen endcase MEMADR: case(op) LB: nextstate = LBRD; SB: nextstate = SBWR; default: nextstate = FETCH1; / should never happen endcase LBRD: nextstate = LBWR; LBWR: nextstate = FETCH1; SBWR: nextstate = FETCH1; RTYPEEX: nextstate = RTYPEW

12、R; RTYPEWR: nextstate = FETCH1; BEQEX: nextstate = FETCH1; JEX: nextstate = FETCH1; default: nextstate = FETCH1; / should never happen endcase end always (*) begin / set all outputs to zero, then conditionally assert just the appropriate ones irwrite = 4b0000; pcwrite = 0; pcwritecond = 0; regwrite

13、= 0; regdst = 0; memread = 0; memwrite = 0; alusrca = 0; alusrcb = 2b00; aluop = 2b00; pcsource = 2b00; iord = 0; memtoreg = 0; case(state) FETCH1: begin memread = 1; irwrite = 4b1000; alusrcb = 2b01; pcwrite = 1; end FETCH2: begin memread = 1; irwrite = 4b0100; alusrcb = 2b01; pcwrite = 1; end FETC

14、H3: begin memread = 1; irwrite = 4b0010; alusrcb = 2b01; pcwrite = 1; end FETCH4: begin memread = 1; irwrite = 4b0001; alusrcb = 2b01; pcwrite = 1; end DECODE: alusrcb = 2b11; MEMADR: begin alusrca = 1; alusrcb = 2b10; end LBRD: begin memread = 1; iord = 1; end LBWR: begin regwrite = 1; memtoreg = 1

15、; end SBWR: begin memwrite = 1; iord = 1; end RTYPEEX: begin alusrca = 1; aluop = 2b10; end RTYPEWR: begin regdst = 1; regwrite = 1; end BEQEX: begin alusrca = 1; aluop = 2b01; pcwritecond = 1; pcsource = 2b01; end JEX: begin pcwrite = 1; pcsource = 2b10; end endcase end assign pcen = pcwrite | (pcw

16、ritecond & zero); / program counter enableendmodulemodule alucontrol(input 1:0 aluop, input 5:0 funct, output reg 2:0 alucont); always (*) case(aluop) 2b00: alucont = 3b010; / add for lb/sb/addi 2b01: alucont = 3b110; / sub (for beq) default: case(funct) / R-Type instructions 6b100000: alucont = 3b0

17、10; / add (for add) 6b100010: alucont = 3b110; / subtract (for sub) 6b100100: alucont = 3b000; / logical and (for and) 6b100101: alucont = 3b001; / logical or (for or) 6b101010: alucont = 3b111; / set on less (for slt) default: alucont = 3b101; / should never happen endcase endcaseendmodulemodule da

18、tapath #(parameter WIDTH = 8, REGBITS = 3) (input clk, reset, input WIDTH-1:0 memdata, input alusrca, memtoreg, iord, pcen, regwrite, regdst, input 1:0 pcsource, alusrcb, input 3:0 irwrite, input 2:0 alucont, output zero, output 31:0 instr, output WIDTH-1:0 adr, writedata); / the size of the paramet

19、ers must be changed to match the WIDTH parameter parameter CONST_ZERO = 8b0; parameter CONST_ONE = 8b1; wire REGBITS-1:0 ra1, ra2, wa; wire WIDTH-1:0 pc, nextpc, md, rd1, rd2, wd, a, src1, src2, aluresult, aluout, constx4; / shift left constant field by 2 assign constx4 = instrWIDTH-3:0,2b00; / regi

20、ster file address fields assign ra1 = instrREGBITS+20:21; assign ra2 = instrREGBITS+15:16; mux2 #(REGBITS) regmux(instrREGBITS+15:16, instrREGBITS+10:11, regdst, wa); / independent of bit width, load instruction into four 8-bit registers over four cycles flopen #(8) ir0(clk, irwrite0, memdata7:0, in

21、str7:0); flopen #(8) ir1(clk, irwrite1, memdata7:0, instr15:8); flopen #(8) ir2(clk, irwrite2, memdata7:0, instr23:16); flopen #(8) ir3(clk, irwrite3, memdata7:0, instr31:24); / datapath flopenr #(WIDTH) pcreg(clk, reset, pcen, nextpc, pc); flop #(WIDTH) mdr(clk, memdata, md); flop #(WIDTH) areg(clk

22、, rd1, a); flop #(WIDTH) wrd(clk, rd2, writedata); flop #(WIDTH) res(clk, aluresult, aluout); mux2 #(WIDTH) adrmux(pc, aluout, iord, adr); mux2 #(WIDTH) src1mux(pc, a, alusrca, src1); mux4 #(WIDTH) src2mux(writedata, CONST_ONE, instrWIDTH-1:0, constx4, alusrcb, src2); mux4 #(WIDTH) pcmux(aluresult,

23、aluout, constx4, CONST_ZERO, pcsource, nextpc); mux2 #(WIDTH) wdmux(aluout, md, memtoreg, wd); regfile #(WIDTH,REGBITS) rf(clk, regwrite, ra1, ra2, wa, wd, rd1, rd2); alu #(WIDTH) alunit(src1, src2, alucont, aluresult); zerodetect #(WIDTH) zd(aluresult, zero);endmodulemodule alu #(parameter WIDTH =

24、8) (input WIDTH-1:0 a, b, input 2:0 alucont, output reg WIDTH-1:0 result); wire WIDTH-1:0 b2, sum, slt; assign b2 = alucont2 ? b:b; assign sum = a + b2 + alucont2; / slt should be 1 if most significant bit of sum is 1 assign slt = sumWIDTH-1; always(*) case(alucont1:0) 2b00: result = a & b; 2b01: re

25、sult = a | b; 2b10: result = sum; 2b11: result = slt; endcaseendmodulemodule regfile #(parameter WIDTH = 8, REGBITS = 3) (input clk, input regwrite, input REGBITS-1:0 ra1, ra2, wa, input WIDTH-1:0 wd, output WIDTH-1:0 rd1, rd2); reg WIDTH-1:0 RAM (1REGBITS)-1:0; / three ported register file / read t

26、wo ports combinationally / write third port on rising edge of clock / register 0 hardwired to 0 always (posedge clk) if (regwrite) RAMwa = wd; assign rd1 = ra1 ? RAMra1 : 0; assign rd2 = ra2 ? RAMra2 : 0;endmodulemodule zerodetect #(parameter WIDTH = 8) (input WIDTH-1:0 a, output y); assign y = (a=0

27、);endmodule module flop #(parameter WIDTH = 8) (input clk, input WIDTH-1:0 d, output reg WIDTH-1:0 q); always (posedge clk) q = d;endmodulemodule flopen #(parameter WIDTH = 8) (input clk, en, input WIDTH-1:0 d, output reg WIDTH-1:0 q); always (posedge clk) if (en) q = d;endmodulemodule flopenr #(par

28、ameter WIDTH = 8) (input clk, reset, en, input WIDTH-1:0 d, output reg WIDTH-1:0 q); always (posedge clk) if (reset) q = 0; else if (en) q = d;endmodulemodule mux2 #(parameter WIDTH = 8) (input WIDTH-1:0 d0, d1, input s, output WIDTH-1:0 y); assign y = s ? d1 : d0; endmodulemodule mux4 #(parameter WIDTH = 8)