1、24毕业设计附录附录一、预处理library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity signed_buma isport (X_in:in std_logic_vector(7 downto 0);-输入 clk:in std_logic;-输入信号50MHz buma:out std_logic_vector(7 downto 0);-补码输出end signed_buma;architecture arc of signed_buma issignal temp:std_logic_v
2、ector(7 downto 0);-中间信号signal b:std_logic;-中间信号beginb=X_in(7);a:process(clk)beginif clkevent and clk=1 then if b=1 then temp=(X_in(7)&(not X_in(6)&(not X_in(5)&(not X_in(4)& (not X_in(3)&(not X_in(2)&(not X_in(1)&(not X_in(0)+1; else temp=X_in; end if ;end if;end process;buma=temp;end arc;二、移位寄存器lib
3、rary ieee;use ieee.std_logic_1164.all;entity delay is -延时port(X_in:in std_logic_vector(7 downto 0);-滤波器输入clk:in std_logic;-输入时钟 a0,a1,a2,a3,a4,a5,a6,a7:buffer std_logic_vector(7 downto 0);-寄存器a8,a9,a10,a11,a12,a13,a14,a15:buffer std_logic_vector(7 downto 0)-寄存器);end delay;architecture one of delay i
4、sbeginprocess(clk)beginif clk event and clk=1then a15=a14; a14=a13; a13=a12; a12=a11; a11=a10; a10=a9; a9=a8; a8=a7; a7=a6; a6=a5; a5=a4; a4=a3; a3=a2; a2=a1; a1=a0; a0=X_in;end if;end process;end one;三、加法与地址码形成单元VHDL代码如下:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;use iee
5、e.std_logic_arith.all; -输入预加和地址码产生entity Address is port(a0,a1,a2,a3,a4,a5,a6,a7:in std_logic_vector(7 downto 0);-输入寄存器a8,a9,a10,a11,a12,a13,a14,a15:in std_logic_vector(7 downto 0);-输入寄存器clk:in std_logic;-输入时钟y0,y1,y2,y3,y4,y5,y6,y7,y8:out std_logic_vector(7 downto 0);-地址输出end Address;architecture a
6、rc of Address issignal b0,b1,b2,b3,b4,b5,b6,b7:std_logic_vector(8 downto 0);begin b0=(a0(0)&a0)+(a8(0)&a8);b1=(a1(0)&a1)+(a9(0)&a9);b2=(a2(0)&a2)+(a10(0)&a10);b3=(a3(0)&a3)+(a11(0)&a11);b4=(a4(0)&a4)+(a12(0)&a12);b5=(a5(0)&a5)+(a13(0)&a13);b6=(a6(0)&a6)+(a14(0)&a14);b7=(a7(0)&a7)+(a15(0)&a15);proces
7、s(clk)beginif clk event and clk=1then-下面产生的8位位矢量将作为LUT的地址 y0=b7(0)&b6(0)&b5(0)&b4(0)&b3(0)&b2(0)&b1(0)&b0(0); y1=b7(1)&b6(1)&b5(1)&b4(1)&b3(1)&b2(1)&b1(1)&b0(1); y2=b7(2)&b6(2)&b5(2)&b4(2)&b3(2)&b2(2)&b1(2)&b0(2); y3=b7(3)&b6(3)&b5(3)&b4(3)&b3(3)&b2(3)&b1(3)&b0(3); y4=b7(4)&b6(4)&b5(4)&b4(4)&b3(4)&b
8、2(4)&b1(4)&b0(4); y5=b7(5)&b6(5)&b5(5)&b4(5)&b3(5)&b2(5)&b1(5)&b0(5); y6=b7(6)&b6(6)&b5(6)&b4(6)&b3(6)&b2(6)&b1(6)&b0(6); y7=b7(7)&b6(7)&b5(7)&b4(7)&b3(7)&b2(7)&b1(7)&b0(7); y8m:=x000;when 0001=m:=x52;when 0010=m:=x4D;when 0011=m:=x9f;when 0100=m:=x23;when 0101=m:=x75;when 0110=m:=x70;when 0111=m:=x
9、c2;when 1000=m:=x2c;when 1001=m:=x7e;when 1010=m:=x79;when 1011=m:=x4f;when 1100=m:=xcb;when 1101=m:=xa1;when 1110=m:=x9c;when 1111=m:=x79;when others=m:=x000;end case;return m;end LUT1;end FIR_ROM1;高四位和低四位LUT输出数据要拼在一起,VHDL代码如下:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;u
10、se ieee.std_logic_arith.all;use work.FIR_ROM1.all;use work.FIR_ROM2.all;use work.FIR_ROM3.all;use work.FIR_ROM4.all;entity firrom isport( ADD0,ADD1,ADD2,ADD3,ADD4:in std_logic_vector(7 downto 0); ADD5,ADD6,ADD7,ADD8:in std_logic_vector(7 downto 0); clk:in std_logic;-输入时钟50MHz f0,f1,f2,f3,f4,f5,f6,f7
11、,f8:out std_logic_vector(12 downto0);end firrom;architecture arc of firrom issignal m0,m1,m2,m3,m4,m5,m6,m7,m8: std_logic_vector(11 downto0); signalm00,m11,m22,m33,m44,m55,m66,m77,m88:std_logic_vector(11 downto 0);begin-下面的语句是把高四位输出和低四位输出拼起来m0=LUT2(ADD0(7 downto 4);m00=LUT1(ADD0(3 downto 0);m1=LUT2(
12、ADD1(7 downto 4);m11=LUT1(ADD1(3 downto 0);m2=LUT2(ADD2(7 downto 4);m22=LUT1(ADD2(3 downto 0);m3=LUT2(ADD3(7 downto 4);m33=LUT1(ADD3(3 downto 0);m4=LUT2(ADD4(7 downto 4);m44=LUT1(ADD4(3 downto 0);m5=LUT2(ADD5(7 downto 4);m55=LUT1(ADD5(3 downto 0);m6=LUT2(ADD6(7 downto 4);m66=LUT1(ADD6(3 downto 0);m7
13、=LUT2(ADD7(7 downto 4);m77=LUT1(ADD7(3 downto 0);m8=LUT2BU(ADD8(7 downto 4);m88=LUT1BU(ADD8(3 downto 0);process(clk)beginif clkevent and clk=1then f0=(m0(11)&m0)+(m00(11)&m00);f1=(m1(11)&m1)+(m11(11)&m11); f2=(m2(11)&m2)+(m22(11)&m22);f3=(m3(11)&m3)+(m33(11)&m33); f4=(m4(11)&m4)+(m44(11)&m44);f5=(m5
14、(11)&m5)+(m55(11)&m55); f6=(m6(11)&m6)+(m66(11)&m66);f7=(m7(11)&m7)+(m77(11)&m77); f8m:=x000;when 0001=m:=xfae;when 0010=m:=xfb3;when 0011=m:=x061;when 0100=m:=xfdd;when 0101=m:=xf58;when 0110=m:=xf5d;when 0111=m:=xf0b;when 1000=m:=xfd4;when 1001=m:=xf82;when 1010=m:=xf87;when 1011=m:=xfb1;when 1100
15、=m:=xf35;when 1101=m:=xf5f;when 1110=m:=xf64;when 1111=m:=xf12;when others=m:=x000;end case;return m;end LUT1BU;end FIR_ROM2;-高四位(低通滤波器)library ieee;use ieee.std_logic_1164.all;package FIR_ROM3 isfunction LUT2(y:in std_logic_vector(3 downto 0) return std_logic_vector;end FIR_ROM3;package body FIR_RO
16、M3 isfunction LUT2(y:in std_logic_vector(3 downto 0) return std_logic_vector isvariable m:std_logic_vector(11 downto 0);begincase y iswhen 0000=m:=x000;when 0001=m:=x095;when 0010=m:=x103;when 0011=m:=x198;when 0100=m:=x15f;when 0101=m:=x1f4;when 0110=m:=x262;when 0111=m:=x1f7;when 1000=m:=x193;when
17、 1001=m:=x228;when 1010=m:=x296;when 1011=m:=x2f2;when 1100=m:=x22b;when 1101=m:=x387;when 1110=m:=x2f5;when 1111=m:=x38a;when others=m:=x000;end case;return m;end LUT2;end FIR_ROM3;-高四位补码(低通滤波器)library ieee;use ieee.std_logic_1164.all;package FIR_ROM4 isfunction LUT2BU(y:in std_logic_vector(3 downt
18、o 0) return std_logic_vector;end FIR_ROM4;package body FIR_ROM4 isfunction LUT2BU(y:in std_logic_vector(3 downto 0) return std_logic_vector isvariable m:std_logic_vector(11 downto 0);begincase y iswhen 0000=m:=x000;when 0001=m:=xf6b;when 0010=m:=xefd;when 0011=m:=xe68;when 0100=m:=xea1;when 0101=m:=
19、xe0c;when 0110=m:=xd9e;when 0111=m:=xd09;when 1000=m:=xe6d;when 1001=m:=xdd8;when 1010=m:=xd6a;when 1011=m:=xd0e;when 1100=m:=xcd5;when 1101=m:=xc79;when 1110=m:=xc6b;when 1111=m:=xb76;when others=m:=x000;end case;return m;end LUT2BU;end FIR_ROM4;五、低4位LTU程序(带通滤波器)library ieee;use ieee.std_logic_1164
20、.all;package FIR_ROM1 isfunction LUT1(y:in std_logic_vector(3 downto 0) return std_logic_vector;end FIR_ROM1;package body FIR_ROM1 isfunction LUT1(y:in std_logic_vector(3 downto 0)return std_logic_vector is variable m:std_logic_vector(11 downto 0);begincase y iswhen 0000=m:=x000;when 0001=m:=x5;when
21、 0010=m:=x14;when 0011=m:=x19;when 0100=m:=x40;when 0101=m:=x45;when 0110=m:=x54;when 0111=m:=x59;when 1000=m:=x80;when 1001=m:=x85;when 1010=m:=x94;when 1011=m:=xc0;when 1100=m:=x99;when 1101=m:=xc5;when 1110=m:=xd4;when 1111=m:=xd9;when others=m:=x000;end case;return m;end LUT1;end FIR_ROM1;-低四位补码
22、(带通滤波器)library ieee;use ieee.std_logic_1164.all;package FIR_ROM2 is-程序包function LUT1BU(y:in std_logic_vector(3 downto 0)-函数体 return std_logic_vector;end FIR_ROM2;package body FIR_ROM2 isfunction LUT1BU(y:in std_logic_vector(3 downto 0) return std_logic_vector isvariable m:std_logic_vector(11 downto
23、0);begincase y iswhen 0000=m:=x000;when 0001=m:=xfae;when 0010=m:=xfb3;when 0011=m:=x061;when 0100=m:=xfdd;when 0101=m:=xf58;when 0110=m:=xf5d;when 0111=m:=xf0b;when 1000=m:=xfd4;when 1001=m:=xf82;when 1010=m:=xf87;when 1011=m:=xfb1;when 1100=m:=xf35;when 1101=m:=xf5f;when 1110=m:=xf64;when 1111=m:=
24、xf12;when others=m:=x000;end case;return m;end LUT1BU;end FIR_ROM2;-高四位(带通滤波器)library ieee;use ieee.std_logic_1164.all;package FIR_ROM3 isfunction LUT2(y:in std_logic_vector(3 downto 0) return std_logic_vector;end FIR_ROM3;package body FIR_ROM3 isfunction LUT2(y:in std_logic_vector(3 downto 0) retur
25、n std_logic_vector isvariable m:std_logic_vector(11 downto 0);begincase y iswhen 0000=m:=x000;when 0001=m:=xcb;when 0010=m:=x122;when 0011=m:=x1ed;when 0100=m:=x161;when 0101=m:=x22c;when 0110=m:=x283;when 0111=m:=x34e;when 1000=m:=x18d;when 1001=m:=x258;when 1010=m:=x2af;when 1011=m:=x2ee;when 1100=m:=x37a;when 1101=m:=x3b9;when 1110=m:=x410;when 1111=m:=x4db;when others=m:=x000;end case;return m;end LUT2;end FIR_ROM3;-高四位补码(带通滤波器)library ieee
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