单片机AT89C52简要说明.docx

1、单片机AT89C52简要说明附录A 英文原文Microcomputer AT89C52 Synoptic ElucidationThe microcomputer AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture,a full duplex serial port, on-chip oscilla

2、tor, and clock circuitry.In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning.

3、The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset,for the figure 1.Pin DescriptionVCC:Supply voltage.GND:Ground.Port 0:Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eigh

4、t TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code byte

5、s during Flash programming and outputs the code bytes during program verification.External pull-ups are required during program verification.Port 1:Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1

6、pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) a

7、nd the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2:Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source

8、four TTL inputs.When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high order address byte during fetches

9、 from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2

10、 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port

11、3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Po

12、rt 3 also receives some control signals for Flash programming and verification.RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG:Address Latch Enable is an output pulse for latching the low byte of the address during accesses to ext

13、ernal memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to ex

14、ternal data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Other- wise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execu

15、tion mode.PSEN:Program Store Enable is the read strobe to external program memory.When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP:External Acces

16、s Enable. EA must be strapped to GND in order to enable the 图A.1 AT89C52方框图device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal pro

17、gram executions.This pin also receives the12-volt programming enable voltage(VPP) during Flash programming when 12-volt programming is selected.XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.Spe

18、cial Function Registers：Not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted loc

19、ations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H,RCAP2L) are the Capture/R

20、eload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priori- ties can be set for each of the six interrupt sources in the IP register.Data Memory:The AT89C52 implements 256 bytes of on-chip

21、 RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR

22、 space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instr

23、uction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1:Timer 0 and Timer 1 in the AT89C52 operate the

24、 same way as Timer 0 and Timer 1 in the AT89C51.Timer 2:Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON.Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rat

25、e generator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the C

26、ounter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is increme

27、nted. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition,the maxi- mum count rate is 1/24 of the oscillator frequency.To ensure tha

28、t a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture Mode:In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. Thi

29、s bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in

30、T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. Auto-Reload (Up or Down Counter):Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upo

31、n reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Timer 2 automatically count up when DCEN = 0. In this mode, two option s are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts

32、 up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software.If EXEN2 = 1, a 16-bit reload can be triggered either by an overf

33、low or by a 1-to-0 transition at external input T2EX. This transi- tion also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2