课设报告数据结构.docx

1、课设报告数据结构计算机组成原理与汇编实验实 验 报 告学生姓名： 王明颖 学 号： 14570131 同组成员： 张伟宸 翟芸婷 完成日期： 2016.7.8 成 绩： 一、实验一1二、实验二13三、实验三18四、实验四31五、心得与体会39六、参考资料39一实验一16位并行进位运算器功能部件的设计与实现（一）总体设计1.1.1问题分析了解并行进位运算器的工作原理和过程，利用多个芯片采用扩展的方式设计出16位并行进位运算器功能部件，并封装调试。1、分析并设计16位并行进位运算器的基本结构；2、选择芯片及若干元器件进行物理连接，完成16位并行进位运算器功能部件的设计，并实现部件的封装；3、对设计

2、出的16位并行进位运算器功能部件进行测试，检查运算器功能部件是否能够正确完成数值运算的功能。运算器（ALU）功能部件是为了完成计算机主机系统设计实践的算术/逻辑运算功能而设计的功能部件，是计算机进行算术/逻辑运算的核心部件。在本范例中设计的运算器功能部件可以对 8 位数据进行算术/逻辑运算。此部件采用了两片 4 位片的 74181，通过串行进位而扩展成 8 位运算器。暂存器(74273)对从总线上面传来的数据进行寄存，可以起到暂存数据的作用。三态门(74244)由控制信号 ALU-BUS 控制，保证 ALU 运算所得到的结果在需要时送上总线，完成算术逻辑运算。1.1.2总体方案设计。 1、设计

3、出部件的逻辑原理图，画出部件的逻辑电路布线图；2、拟定测试数据及测试方法；3、检测模拟仿真测试结果的正确性；4、对设计出的部件进行封装，并写出封装后芯片的功能表。（二）详细设计1.2.1每个模块的功能完成运算1.2.2入出信息输入信息 输出信息 1.2.3处理逻辑1.2.4屏幕显示布局设计图74181功能表74182功能表运算器封装布局设计图（3）程序编码。- Copyright (C) 1991-2008 Altera Corporation- Your use of Altera Corporations design tools, logic functions - and other

4、software and tools, and its AMPP partner logic - functions, and any output files from any of the foregoing - (including device programming or simulation files), and any - associated documentation or information are expressly subject - to the terms and conditions of the Altera Program License - Subsc

5、ription Agreement, Altera MegaCore Function License - Agreement, or other applicable license agreement, including, - without limitation, that your use is for the sole purpose of - programming logic devices manufactured by Altera and sold by - Altera or its authorized distributors. Please refer to th

6、e - applicable agreement for further details.- PROGRAM Quartus II 64-Bit- VERSION Version 8.0 Build 215 05/29/2008 SJ Full VersionLIBRARY ieee;USE ieee.std_logic_1164.all; LIBRARY work;ENTITY Block1 IS port ( cn : IN STD_LOGIC; m : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(15 downto 0); b : IN STD_LOGIC

7、_VECTOR(15 downto 0); s : IN STD_LOGIC_VECTOR(3 downto 0); f : OUT STD_LOGIC_VECTOR(15 downto 0) );END Block1;ARCHITECTURE bdf_type OF Block1 ISattribute black_box : boolean;attribute noopt : boolean;component 74181_0 PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGI

8、C; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F

9、2N : OUT STD_LOGIC);end component;attribute black_box of 74181_0: component is true;attribute noopt of 74181_0: component is true;component 74181_1 PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN

10、STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_1: comp

11、onent is true;attribute noopt of 74181_1: component is true;component 74181_2 PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S

12、1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_2: component is true;attribute noopt of 74181_2: component is true;component

13、74181_3 PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_L

14、OGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_3: component is true;attribute noopt of 74181_3: component is true;component 74182_4 PORT(PN2 : IN STD_LOGIC; GN2 : IN STD_LOGIC; GN3 : IN STD_LOGI

15、C; PN3 : IN STD_LOGIC; CI : IN STD_LOGIC; PN1 : IN STD_LOGIC; PN0 : IN STD_LOGIC; GN1 : IN STD_LOGIC; GN0 : IN STD_LOGIC; CY : OUT STD_LOGIC; CX : OUT STD_LOGIC; CZ : OUT STD_LOGIC);end component;attribute black_box of 74182_4: component is true;attribute noopt of 74182_4: component is true;signal f

16、_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(15 downto 0);signal SYNTHESIZED_WIRE_0 : STD_LOGIC;signal SYNTHESIZED_WIRE_1 : STD_LOGIC;signal SYNTHESIZED_WIRE_2 : STD_LOGIC;signal SYNTHESIZED_WIRE_3 : STD_LOGIC;signal SYNTHESIZED_WIRE_4 : STD_LOGIC;signal SYNTHESIZED_WIRE_5 : STD_LOGIC;signal SYNTHESIZED_W

17、IRE_6 : STD_LOGIC;signal SYNTHESIZED_WIRE_7 : STD_LOGIC;signal SYNTHESIZED_WIRE_8 : STD_LOGIC;signal SYNTHESIZED_WIRE_9 : STD_LOGIC;signal SYNTHESIZED_WIRE_10 : STD_LOGIC;BEGIN b2v_inst : 74181_0PORT MAP(B0N = b(0), A0N = a(0), A1N = a(1), B1N = b(1), A3N = a(3), B2N = b(2), A2N = a(2), M = m, CN =

18、cn, B3N = b(3), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_WIRE_6, GN = SYNTHESIZED_WIRE_5, F3N = f_ALTERA_SYNTHESIZED(3), F1N = f_ALTERA_SYNTHESIZED(1), F0N = f_ALTERA_SYNTHESIZED(0), F2N = f_ALTERA_SYNTHESIZED(2);b2v_inst1 : 74181_1PORT MAP(B0N = b(4), A0N = a(4), A1N = a(5), B1N

19、 = b(5), A3N = a(7), B2N = b(6), A2N = a(6), M = m, CN = SYNTHESIZED_WIRE_0, B3N = b(7), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_WIRE_3, GN = SYNTHESIZED_WIRE_4, F3N = f_ALTERA_SYNTHESIZED(7), F1N = f_ALTERA_SYNTHESIZED(5), F0N = f_ALTERA_SYNTHESIZED(4), F2N = f_ALTERA_SYNTHESIZ

20、ED(6);b2v_inst2 : 74181_2PORT MAP(B0N = b(8), A0N = a(8), A1N = a(9), B1N = b(9), A3N = a(11), B2N = b(10), A2N = a(10), M = m, CN = SYNTHESIZED_WIRE_1, B3N = b(11), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_WIRE_7, GN = SYNTHESIZED_WIRE_9, F3N = f_ALTERA_SYNTHESIZED(11), F1N = f_

21、ALTERA_SYNTHESIZED(9), F0N = f_ALTERA_SYNTHESIZED(8), F2N = f_ALTERA_SYNTHESIZED(10);b2v_inst3 : 74181_3PORT MAP(B0N = b(12), A0N = a(12), A1N = a(13), B1N = b(13), A3N = a(15), B2N = b(14), A2N = a(14), M = m, CN = SYNTHESIZED_WIRE_2, B3N = b(15), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SY

22、NTHESIZED_WIRE_8, GN = SYNTHESIZED_WIRE_10, F3N = f_ALTERA_SYNTHESIZED(15), F1N = f_ALTERA_SYNTHESIZED(13), F0N = f_ALTERA_SYNTHESIZED(12), F2N = f_ALTERA_SYNTHESIZED(14);b2v_inst4 : 74182_4PORT MAP(PN2 = SYNTHESIZED_WIRE_3, GN2 = SYNTHESIZED_WIRE_4, GN3 = SYNTHESIZED_WIRE_5, PN3 = SYNTHESIZED_WIRE_

23、6, CI = cn, PN1 = SYNTHESIZED_WIRE_7, PN0 = SYNTHESIZED_WIRE_8, GN1 = SYNTHESIZED_WIRE_9, GN0 = SYNTHESIZED_WIRE_10, CY = SYNTHESIZED_WIRE_1, CX = SYNTHESIZED_WIRE_2, CZ = SYNTHESIZED_WIRE_0);f = f_ALTERA_SYNTHESIZED;END; （四）遇到的问题及解决方法分析遇到的问题：进位怎样传入。解决办法：通过74182芯片来传输进位。（五）尚未解决的问题及其应对策略尚未解决的问题：运算结果总比

24、实际结果多一应对策略：S0S3的赋值不同所运行的运算不同，可以通过改变S0S3的赋值来解决。二实验二带字位扩展存储器功能部件的设计与实现（一）总体设计2.1.1问题分析了解随机存储器的工作原理和过程，熟悉随机存储器的读写原理。根据存储器的工作原理，并且按照存储器字位扩展的基本原则完成存储器功能部件的设计，并实现器件封装，测试存储器的读写功能。1、设计出存储器功能部件的基本结构；2、选择芯片及若干元器件进行物理连接，完成存储器部件的设计并实现部件的封装；3、对该部件进行模拟仿真测试，检查存储器功能部件的数据读写是否正确。功能介绍： 存储器功能部件（Memory）是为了提供存储数据和程序而设计的功

25、能部件。可作为主机系统的主存储器使用。 在存储器功能部件中，设计了主存地址寄存器（MAR）和主存数据寄存器（MDR），作为主存与 CPU 进行数据交换的接口。MAR 接收、暂存总线上的主存地址，MDR 暂存输出到总线上的数据。 CPMAR 和 CPMDR 管脚分别作为主存地址寄存器（MAR）和主存数据寄存器（MDR）的数据接收控制信号。RD 作为存储器的读控制信号（上升沿触发），在 RD 为高电位 (即：存储器数据输出有效) 期间，应发出 CPMDR 脉冲控制信号，使存储器的读出数据锁存到存储器数据寄存器 MDR 中。WR 和 WRE 分别作为存储器的写控制信号和写使能控制信号，在 WRE为高

26、电位期间，发出 WR 脉冲控制信号（上升沿有效），则可以把输入数据写入到主存储器中。RAM-BUS 控制信号（低电位有效）完成将存储器的输出数据通过三态门输出的功能。2.1.2总体方案设计。 1、设计出部件的逻辑原理图，画出部件的逻辑电路布线图；2、拟定测试数据及测试方法；3、检测模拟仿真测试结果的正确性；4、对设计出的部件进行封装，并写出封装后芯片的功能表。（二）详细设计2.2.1每个模块的功能具有扩展功能的存储器 存储功能2.2.2处理逻辑 2.2.3屏幕显示布局设计图74273功能表74244功能表存储器封装布局设计图（3）程序编码。/ Copyright (C) 1991-2008 A

27、ltera Corporation/ Your use of Altera Corporations design tools, logic functions / and other software and tools, and its AMPP partner logic / functions, and any output files from any of the foregoing / (including device programming or simulation files), and any / associated documentation or informat

28、ion are expressly subject / to the terms and conditions of the Altera Program License / Subscription Agreement, Altera MegaCore Function License / Agreement, or other applicable license agreement, including, / without limitation, that your use is for the sole purpose of / programming logic devices m

29、anufactured by Altera and sold by / Altera or its authorized distributors. Please refer to the / applicable agreement for further details./ PROGRAM Quartus II 64-Bit/ VERSION Version 8.0 Build 215 05/29/2008 SJ Full Versionmodule Block12( WRE, WR, RD, clka, clkd, CLRN, GN, a, in, out);input WRE;input WR;input RD;input clka;input clkd;input CLRN;input GN