EDA考试程序.docx

1、EDA考试程序EDA考试常用程序1：用VHDL语言设计2选1多路选择器。ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT );END ENTITY mux21a;ARCHITECTURE one OF mux21a IS BEGIN y a2,b=a3,s=s0,y=tmp); U2 : mux21a PORT MAP ( a=a1,b=tmp,s=s1,y=outy);END ARCHITECTURE one;实验二 时序逻辑电路的VHDL设计3：用VHDL语言设计D边沿触发器。LIBRARY IEEE ;USE IEEE.STD_LO

2、GIC_1164.ALL ;ENTITY DFF1 IS PORT ( CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q : OUT STD_LOGIC );END ;ARCHITECTURE bhv OF DFF1 IS SIGNAL Q1 : STD_LOGIC ;BEGIN PROCESS ( CLK,Q1) BEGIN IF CLKEVENT AND CLK = 1 THEN Q1 = D ; END IF; END PROCESS ;Q =Q1 ;END bhv ;4：用VHDL语言设计D锁存器。LIBRARY IEEE ;USE IEEE.STD_

3、LOGIC_1164.ALL ;ENTITY DFF3 IS PORT ( CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q : OUT STD_LOGIC );END ;ARCHITECTURE bhv OF DFF3 ISBEGIN PROCESS ( CLK,D) BEGIN IF CLK = 1 THEN Q 0); ELSIF CLKEVENT AND CLK=1 THEN IF EN = 1 THEN IF CQI 0); END IF; END IF; END IF; IF CQI = 9 THEN COUT = 1; ELSE COUT = 0

4、; END IF;CQ 0); ELSIF CLKEVENT AND CLK=1 THEN IF EN = 1 THEN IF UD = 0THEN IF CQI 0); END IF; END IF; IF UD = 1THEN IF CQI = 0 THEN CQI := 1001; ELSIF CQI 10 THEN CQI := CQI - 1; ELSE CQI := 1001; -END IF; END IF; END IF; END IF; END IF; IF UD = 0THEN IF CQI = 9 THEN COUT = 1; ELSE COUT = 0; END IF;

5、 END IF; IF UD =1THEN IF CQI = 0 THEN COUT = 1; ELSE COUT = 0; END IF; END IF;CQ LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S NULL ; END CASE; END PROCESS;8：用VHDL语言描述图4.1所示计数、译码显示电路。（DEC）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UN

6、SIGNED.ALL;ENTITY DEC IS PORT (CLK0,RST0,ENA0 : IN STD_LOGIC; LED : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); COUT0 : OUT STD_LOGIC );END DEC;ARCHITECTURE ONE OF DEC IS COMPONENT CNT16 IS PORT (CLK,RST,ENA : IN STD_LOGIC; CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUTY : OUT STD_LOGIC ); END COMPONENT ; COMPONE

7、NT DECL7S IS PORT (A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT ; SIGNAL TMP : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN U1 : CNT16 PORT MAP(CLK=CLK0,RST=RST0,ENA=ENA0,CQ=TMP,COUTY=COUT0); U2 : DECL7S PORT MAP(A =TMP,LED7S = LED);END;（CNT16）LIBRARY IEEE;USE I

8、EEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT16 IS PORT (CLK,RST,ENA : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUTY : OUT STD_LOGIC );END CNT16;ARCHITECTURE BEHAV OF CNT16 ISBEGIN PROCESS ( CLK,RST,ENA ) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST = 1

9、THEN CQI := (OTHERS =0); ELSIF CLKEVENT AND CLK=1 THEN IF ENA = 1 THEN IF CQI 0); END IF; END IF; END IF; IF CQI = 15 THEN COUTY = 1; ELSE COUTY = 0; END IF;CQ 0); ELSIF CLKEVENT AND CLK=1 THEN IF EN = 1 THEN IF CQI 0); END IF; END IF; END IF; IF CQI = 7 THEN COUT = 1; ELSE COUT = 0; END IF;PASS= CQ

10、I;END PROCESS js;AI=PASS; sm : PROCESS (AI) BEGIN IF AI = 000 THEN K = 00000001; ELSIF AI = 001 THEN K = 00000010; ELSIF AI = 010 THEN K = 00000100; ELSIF AI = 011 THEN K = 00001000; ELSIF AI = 100 THEN K = 00010000; ELSIF AI = 101 THEN K = 00100000; ELSIF AI = 110 THEN K = 01000000; ELSE K = 100000

11、00; END IF;END PROCESS sm;A LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S NULL ; END CASE; END PROCESS xs;END one;10：修改实验内容1的程序，增加8个4位锁存器作为输出显示数据缓冲器，由外部输入8个待显示的十六进制数。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SMSC

12、XS ISPORT ( AI: INOUT STD_LOGIC_VECTOR( 2 DOWNTO 0); -CLK : IN STD_LOGIC ; CLK0,CLK1,CLK2 : IN STD_LOGIC; D0 : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); A : INOUT STD_LOGIC_VECTOR( 3 DOWNTO 0); -A : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); K : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -COUT : OUT STD_LOGIC; LED7S : OUT ST

13、D_LOGIC_VECTOR( 6 DOWNTO 0); -Q0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE one OF SMSCXS ISCOMPONENT D4 PORT( CLK : IN STD_LOGIC ; D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END COMPONENT;SIGNAL PASS : STD_LOGIC_VECTOR( 2 DOWNTO 0);SIGNAL P0,P1,P2,P3,P4,P5

14、,P6,P7 : STD_LOGIC_VECTOR( 3 DOWNTO 0);SIGNAL D1,D2,D3,D9,D5,D6,D7,D8 : STD_LOGIC_VECTOR( 3 DOWNTO 0);BEGINSC : PROCESS ( CLK2 ) VARIABLE QI : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN -IF RST = 1 THEN CQI := (OTHERS =0); IF CLK2EVENT AND CLK2=1 THEN -IF EN = 1 THEN IF QI 0); END IF; -END IF; END IF; -IF

15、CQI = 7 THEN COUT = 1; -ELSE COUT = 0; -END IF; -PASS D1 D2 D3 D9 D5 D6 D7 D8 NULL; END CASE; END PROCESS SC;U1 : D4 PORT MAP(CLK=CLK1,D=D1,Q=P0);U2 : D4 PORT MAP(CLK=CLK1,D=D2,Q=P1);U3 : D4 PORT MAP(CLK=CLK1,D=D3,Q=P2);U4 : D4 PORT MAP(CLK=CLK1,D=D9,Q=P3);U5 : D4 PORT MAP(CLK=CLK1,D=D5,Q=P4);U6 : D

16、4 PORT MAP(CLK=CLK1,D=D6,Q=P5);U7 : D4 PORT MAP(CLK=CLK1,D=D7,Q=P6);U8 : D4 PORT MAP(CLK=CLK1,D=D8,Q=P7); js : PROCESS ( CLK0 ) VARIABLE CQI : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN -IF RST = 1 THEN CQI := (OTHERS =0); IF CLK0EVENT AND CLK0=1 THEN -IF EN = 1 THEN IF CQI 0); END IF; -END IF; END IF; -IF

17、 CQI = 7 THEN COUT = 1; -ELSE COUT = 0; -END IF; PASS= CQI; END PROCESS js;AI=PASS; sm : PROCESS (AI) BEGIN IF AI = 000 THEN K = 00000001;A=P0; ELSIF AI = 001 THEN K = 00000010;A=P1; ELSIF AI = 010 THEN K = 00000100;A=P2; ELSIF AI = 011 THEN K = 00001000;A=P3; ELSIF AI = 100 THEN K = 00010000;A=P4; ELSIF AI = 101 THEN K = 00100000;A=P5; ELSIF AI = 110 THEN K = 01000000;A=P6; ELSE K = 10000000;A LED7S LED7S = 000