1、第六章第六章第六章第六章 寄生参数寄生参数寄生参数寄生参数寄生电容 寄生电阻 寄生电感器件的寄生参数 school of phyebasics of ic layout design1school of phyebasics of ic layout design2n n三种主要的寄生参数:三种主要的寄生参数:寄生电容寄生电容 寄生电阻寄生电阻 寄生电感寄生电感n nparameter scalingparameter scaling:conductances and capacitances scale linearly with width conductances and capacit
2、ances scale linearly with width (”widening a wire leads to widening a wire leads to less than a proportional increaseless than a proportional increase in capacitancein capacitance,but,but a proportional reduce in resistancea proportional reduce in resistance,so,so the the RC delay product improvesRC
3、 delay product improves.”“P219,CMOS VLSIP219,CMOS VLSI”)resistances scale inversely with width resistances scale inversely with width interconnects introduce extra resistance,capacitance,and interconnects introduce extra resistance,capacitance,and delay,degrade of large device performance!delay,degr
4、ade of large device performance!need many fingers connected in parallelneed many fingers connected in parallel 寄生电容寄生电容school of phyebasics of ic layout design3n导线之间(同层/不同层)、导线与衬底之间都存在平面电容;上层导线到下层导线、下层导线到衬底之间存在边缘电容。寄生电容寄生电容Capacitance is everywhere.Everything is talking to everything else.school of
5、phyebasics of ic layout design4n由于尺寸很小,因此这些寄生参数的值也很小。对于对电容不敏感的电路,不必担心;不管是CMOS还是双极型,只要涉及高频,寄生会成为问题。n忽略寄生参数会毁掉你的芯片。忽略寄生参数会毁掉你的芯片。导线尽可能短n减少寄生电容的方法:采用电容最低的金属层 绕过电路走线寄生电容寄生电容school of phyebasics of ic layout design5n减少寄生电容的方法-选择金属层n起主要作用的电容通常是导线与衬底间的电容。n如下图,寄生参数可以把电路1的噪声通过衬底耦合到电路2,所以要设法使所有的噪声都远离衬底。寄生电容寄生
6、电容school of phyebasics of ic layout design6n减少寄生电容的方法-选择金属层n可以通过改变金属层来获得较小的至衬底的电容,通常最高金属层所形成的电容总是最小的。n另外值得注意的是并不是所有工艺的最高层金属与衬底产生的寄生电容都最小,它还与金属层的宽度等其它因素有关。有些工艺中或许是 M2对地的电容要比 M4的对地电容大,所以我们不能只凭直觉来判断,一定要通过具体的计算来确认。寄生电容寄生电容MetalMetalM1M1M2M2M3M3M4M4Min.WidthMin.Width0.80.80.80.82.42.46.56.5Cap/Unit AreaC
7、ap/Unit Area (fF/um (fF/um2 2)5 53 32.52.51.51.5Cap 10um wireCap 10um wire40402424666697.597.5school of phyebasics of ic layout design7n减少寄生电容的方法-选择金属层nModern processes have six or more metal layers.n nThe lower layersThe lower layers are thin and optimized for a tight routing pitch.Middle layersMid
8、dle layers are often slightly thicker for lower resistance and better current-handling capability.Upper layersUpper layers may be even thicker to provide a low-resistance power grid and fast global interconnect.寄生电容寄生电容LayerLayerPurposePurposeMetal 1Metal 1Interconnect within cellsInterconnect withi
9、n cellsMetal 2/3Metal 2/3Interconnect between cells within unitsInterconnect between cells within unitsMetal 4/5Metal 4/5Interconnect between units,critical signalsInterconnect between units,critical signalsMetal 6Metal 6I/O pads,clock,power,groundI/O pads,clock,power,groundschool of phyebasics of i
10、c layout design8n减少寄生电容的方法-选择金属层n nwidening a wire leads to widening a wire leads to less than a proportional less than a proportional increase in capacitanceincrease in capacitance,but,but a proportional reduce in a proportional reduce in resistanceresistance,so the,so the RC delay product improves
11、RC delay product improves.nWidening wires also increase the fraction of capacitance the fraction of capacitance of the top and bottom platesof the top and bottom plates,which somewhat reduces reduces coupling noisecoupling noise from adjacent wires.nIncreasing spacing between wires reduces capacitan
12、ce reduces capacitance to the adjacent wiresto the adjacent wires and leaves resistance unchangedresistance unchanged.This improve the RC delayimprove the RC delay to some extent and significantly reduces coupling noise.reduces coupling noise.寄生电容寄生电容school of phyebasics of ic layout design9n减少寄生电容的
13、方法 绕过电路走线n在某些电路的上面布金属线,这是在数字自动布局布线中经常会遇到的情况。各层金属相互交叠,所以在反相器、触发器等都存在寄生电容。如果不加以干预的话,只是由布线器来操作,那么就有可能毁了你的芯片。n在模拟电路版图设计中,我们经常会人为的将敏感信号隔离开来,尽量避免在敏感电路上面走线,而只是将金属线走在电路之间,这样寄生的参数就小一些且相对容易控制。n在数字版图中,90%的导线一起布置,不必关心它们的功能;n而在模拟版图中,对于某些功能可以不在乎寄生电容,而另一些必须注意。寄生电容寄生电容school of phyebasics of ic layout design10n减少寄生
14、电容的方法 绕过电路走线寄生电容寄生电容school of phyebasics of ic layout design11n通过电流密度可以选择导线宽度,电流大小孩影响单元间的布线方案。n翻开工艺手册,我们经常能看到每层金属线能够承载的电流。通过这个参数我们可以计算所需要的金属层宽度。例如,有一根信号线需要承载 1毫安的电流,而工艺手册注明每微米可以走 0.5毫安的电流,那么这根金属层的宽度至少要2微米。寄生电阻寄生电阻school of phyebasics of ic layout design12nIR压降:n假设导线的方块电阻Rsqu是0.05,则 R=Rsqu*L/W =0.05*
15、(2mm/2um)=50 V=IR =50*1mA =50 mV 所以计算得知电压为50毫伏。它对于一个电压非常敏感的电路来讲就会有很大的影响。如果这条导线的压降不能超过10毫伏,显然这个设计就是失败的。所以这就意味着我们必须增加导线宽度才能满足这一要求。寄生电阻寄生电阻school of phyebasics of ic layout design13n为了降低寄生电阻,就需要确保使用最厚的金属层。正如我们了解的,一般情况下,最厚的金属线具有最低的方块电阻。如果遇到相同的金属层厚度,也可以将这几条金属重叠形成并联结构,大大降低了电阻。因此,并联布线是降低大电流路径电阻的有效方法,而且还能节省
16、一定的面积。寄生电阻寄生电阻school of phyebasics of ic layout design14n当电路是在一个真正的高频的情况下工作时,导线也开始存在了电感效应。解决寄生电感的方法就是试着去模拟它,把它当成电路中的一部分。n首先需要尽早的完成布局,好让电路设计者较早的看到导线究竟能有多长,然后估计出可能引起的电感。版图设计过程中尤其注意不要因为电感耦合而影响其它部分。能否利用寄生参数?能否利用寄生参数?n从整体来说,不可以利用寄生参数得到好处。因为寄生参数可以正负相差50%,无法很好地控制。然而,可以利用寄生参数得到一点小外快。如把电源线和地线互相层叠起来就可以得到免费的电源去耦电容。寄生电感寄生电感school of phyebasics of ic layout design15nCMOS晶体管晶体管nMOS器件本身存在两种电容:栅电容栅电容栅电容栅电容和扩散电容扩散电容扩散电容扩散电容。栅电容栅电容栅电容栅电容:平行板电容:Cgb=Cunit/area x A 源漏交叠电容:Cgs、Cgd 总的栅电容:Cg=Cgb+Cgs+Cgd 器件的寄生参数器件的寄生参数o
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