程序分析.docx

1、程序分析1. 1. 分析下面程序，说出该程序的功能。Entity test is generic(setup_time: time := 5ns); port(D:in std_logic; Q:out std_logic; clk : in std_logic);end test;architecture test of test isbegin process(clk) begin if clk=1 and clkevent then assert(Dlast_event setup_time) report “ setup violation” severity error; end i

2、f ; end test;2. 2. 分析下面程序，说出该程序的功能。library IEEE;use IEEE.STD_LOGIC_1164.all;entity s_machine is port( clk : in STD_LOGIC; rst : in STD_LOGIC; din : in STD_LOGIC; comb_output : out STD_LOGIC );end s_machine;architecture s_machine of s_machine istype states is (st0,st1,st2,st3);signal cur_state,next_s

3、tate : states;begin process(clk,rst) begin if rst=1 then cur_state=st0; elsif clkevent and clk=1 then cur_statecomb_output=0; if din=1 then next_state=st1; else next_statecomb_output=0; if din=1 then next_state=st2; else next_state if din=1 then next_state=st3; comb_output=1; else next_state=st0; co

4、mb_output if state_input=1 then next_state=st3; comb_output=1; else next_state=st0; comb_output=0; end if; end case; end process;end s_machine;3. 3. 分析下面程序，指出该程序的功能。process(a,dr,en)beginif en=0 and dr=1 then bout=a;else bout=ZZZZZZZZ;end if;b=bout;end process;process(a,dr,en)beginif en=0 and dr=0 th

5、en aout=b;else aout=ZZZZZZZZ;end if;a=aout;end process;4. 4. 分析下面程序，指出电路功能。library IEEE;use IEEE.STD_LOGIC_1164.all;entity shift is port(clk : in STD_LOGIC; a: in STD_LOGIC; b : out STD_LOGIC);end shift;architecture shift of shift isbegincomponent dff port (d,clk: in std_logic; q: out std_logic);end

6、 component ;signal z:std_logic_vector(0 to 4);begin z(0)=a; g1:for i in 0 to 3 generate dffx:dff port map (z(i),clk,z(i+1); end generate; b=z(4);end shift;5.分析下面程序，所明该程序的功能。library IEEE;use IEEE.STD_LOGIC_1164.all;entity chk is port( din : in STD_LOGIC; clk,clr : in STD_LOGIC; d : in STD_LOGIC_VECTO

7、R(7 downto 0); check_out : out STD_LOGIC );end chk;architecture chk of chk issignal q: integer range 0 to 8;begin process(clk,clr) begin if clr=1 then q if din=d(7) then q=1; else q if din=d(6) then q=2; else q if din=d(5) then q=3; else q if din=d(4) then q=4; else q if din=d(3) then q=5; else q if

8、 din=d(2) then q=6; else q if din=d(1) then q=7; else q if din=d(0) then q=8; else qq=0; end case; end if; end process;process(q)begin if q=8 then check_out=1; else check_out=0; end if; end process;end chk;6.分析下面程序，所明该程序的功能。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ent

9、ity pulse is port ( clk,rst : in std_logic; d : in std_logic_vector(7 downto 0); fout : out std_logic );end pulse;architecture one of pulse issignal full : std_logic;signal cnt8 : std_logic_vector(7 downto 0);signal fout_tmp: std_logic;begin p_reg: process(clk)begin if rst=1 then cnt81); full=0;elsi

10、f clkevent and clk = 1 then if cnt8 = 11111111 then cnt8 = d; -当cnt8计数计满时，输入数据d被预置给计数器cnt8 full = 1; -同时使溢出标志信号full输出为高电平 else cnt8 = cnt8 + 1; -否则继续作加1计数 full = 0; -且输出溢出标志信号full为低电平 end if; end if;end process p_reg ;p_div: process(full) begin if rst=1 then fout_tmp=0; elsif fullevent and full = 1

11、then fout_tmp= not fout_tmp;-如果full为高电平，d触发器输出取反 end if;end process p_div ; foutyyyyy=Z; end case;end process;end nand2;8.分析下面程序，说明其功能。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 ISPORT(input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);sel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);y: out STD_LOGIC);END mux4;A

12、RCHITECTURE rtl OF mux4 IS BEGINPROCESS(input,sel) BEGINIF sel=”00” THENy=input(0);ELSIF sel=”01” THEN y=input(1); ELSIF sel=”10” THEN y=input(2);ELSEyyyyyy=Z; end case;end process;end test;10.分析下面程序，说明其功能。library IEEE;use IEEE.STD_LOGIC_1164.all;entity half_adder is port( a : in STD_LOGIC; b : in S

13、TD_LOGIC; s : out STD_LOGIC; co : out STD_LOGIC );end half_adder;architecture half_adder of half_adder issignal c,d:std_logic;begin c=a or b; d=a nand b; co=not d; s=c and d;end half_adder;library IEEE;use IEEE.STD_LOGIC_1164.all;entity test is port( a,b,cin : in STD_LOGIC; co,s : out STD_LOGIC);end

14、 test;architecture test of test iscomponent half_adder port( a,b : in STD_LOGIC; s,co : out STD_LOGIC );end component ;signal u0_co,u0_s,u1_co:std_logic;begin u0:half_adder port map(a,b,u0_s,u0_co); u1:half_adder port map(u0_s,b,cin,s,u1_co); co=u0_co or u1_co;end test;11.分析下面的VHDL源程序，说明设计电路的功能。libr

15、ary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity lx3_1 isport( s2,s1,s0: in std_logic; d3,d2,d1,d0: in std_logic; d7,d6,d5,d4: in std_logic; y: out std_logic);end lx3_1;architecture one of lx3_1 issignal s:std_logic_vector(2 downto 0);begin s=s2&s1&s0; y=d0 when s=000 else

16、 d1 when s=001 else d2 when s=010 else d3 when s=011 else d4 when s=100 else d5 when s=101 else d6 when s=110 else d7;end one;12分析下面的VHDL源程序，说明设计电路的功能。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity lx3_2 is port( a: in std_logic_vector(3 downto 0); b: in std_logic_ve

17、ctor(3 downto 0); gt,lt,eq: out std_logic);end lx3_2;architecture one of lx3_2 isbegin process(a,b) begin gt=0; lt=0; eqb then gt=1; elsif ab then lt=1; else eq=1; end if; end process;end one;13分析下面的VHDL源程序，说明设计电路的功能。library ieee;use ieee.std_logic_1164.all;entity lx3_3 is port(abin: in std_logic_ve

18、ctor(7 downto 0); din: in std_logic_vector(7 downto 0); dout: out std_logic_vector(7 downto 0);end lx3_3;architecture one of lx3_3 isbegin process(abin,din) begin for i in 0 to 7 loop dout(i)=din(i) and abin(i); end loop; end process;end one;14分析下面的VHDL源程序，说明设计电路的功能。library ieee;use ieee.std_logic_1

19、164.all;use ieee.std_logic_unsigned.all;entity lx3_4 is port( clk: in std_logic; j,k: in std_logic; q,qn: out std_logic);end lx3_4;architecture struc of lx3_4 is signal q_temp:std_logic:=0; signal jk:std_logic_vector(1 downto 0);begin jkq_tempq_tempq_tempq_tempq_temp=X; end case; end if; q=q_temp; q

20、n=not q_temp; end process;end struc;15. 分析下面VHDL源程序，分别给出tim1tim9的值。Architecture time of time is Type tim is (sec,min,hous,day,month,year); Subtype reverse_tim is Tim range month downto min; Signal tim1,tim2,tim3,tim4,tim5,tim6,tim7,tim8:time; begin tim1=timleft; Tim2 =timright; Tim3 =timhigh; Tim4 =

21、timlow ; Tim5 = reverse_timleft; Tim6 = reverse_ timright; Tim7 = reverse_ timhigh; tim8 = reverse_ timlow; tim9=timlength;End time;16.分析下面程序，说出该程序的功能。LIBRARY IEEE;USE IEEE.std_logic_1164.all ;ENTITY sels IS PORT(d，clk:IN STD_LOGIC; q, nq: OUT STD_LOGIC);END sels;IF clk= 1 AND clkEVENT THEN q = d;Nq

22、=NOT q;END IF;17.分析下面程序，说出该程序的功能。library IEEE;use IEEE.STD_LOGIC_1164.all;entity s_machine is port( clk : in STD_LOGIC; rst : in STD_LOGIC; din : in STD_LOGIC; comb_output : out STD_LOGIC );end s_machine;architecture s_machine of s_machine istype states is (st0,st1,st2,st3);signal cur_state,next_sta

23、te : states;begin process(clk,rst) begin if rst=1 then cur_state=st0; elsif clkevent and clk=1 then cur_statecomb_output=0; if din=1 then next_state=st1; else next_statecomb_output=0; if din=1 then next_state=st2; else next_state if din=1 then next_state=st3; comb_output=1; else next_state=st0; comb_output if state_input=1 then next_state=st3; comb_output=1; else next_state=st0; comb_output=0; end if; end case; end process;end s_machine;18.分析下面程序，指出该程序的功能。L