计算机设计与实践 CPU 代码含19条指令.docx

1、计算机设计与实践 CPU 代码含19条指令时钟管理模块entity clk_ctrl isport( Clk:in std_logic; Rst:in std_logic; k:out std_logic_vector(3 downto 0);end clk_ctrl;architecture Behavioral of clk_ctrl is signal tmp:std_logic_vector(3 downto 0);begin process(Clk,Rst,tmp) begin if Rst =1 then -rst=1复位; -k=0000; tmp=0001; elsif Clk

2、=1 and Clkevent then tmp(0)=tmp(3); tmp(3 downto 1)=tmp(2 downto 0); end if; end process; k=tmp;end Behavioral;取指模块entity irget is Port ( Rst : in STD_LOGIC;-复位； Pcback : in STD_LOGIC_VECTOR (15 downto 0);-PC回写； Pcbacka : in STD_LOGIC;-PC回写允许； k1 : in STD_LOGIC;-时钟控制； Order : in STD_LOGIC_VECTOR (15

3、 downto 0);-指令 Pcout : out STD_LOGIC_VECTOR (15 downto 0);-PC输出； Orderout : out STD_LOGIC_VECTOR (15 downto 0);-指令输出； AddrFlag : out STD_LOGIC);-访址标志end irget;architecture Behavioral of irget is signal tmpPC: std_logic_vector (15 downto 0); -指令地址； signal IR:std_logic_vector(15 downto 0);-指令寄存器；begin

4、 process(Rst,Pcback,Pcbacka,k1,order,tmpPc) begin if Rst=1 then tmpPc=0000000000000000; elsif k1=1 then Pcout=tmpPc; AddrFlag=1;-第一个节拍高电平取指； elsif Pcbacka=1 then tmpPc=Pcback;-pc回写允许 -end if; -AddrFlag=0; else AddrFlag=0; end if ; Orderout=Order;-指令存入指令寄存器； end process; -Orderout=IR;-得到指令，准备送往后面的模块；

5、 end Behavioral;运算模块entity CPU_operation is Port ( k2 : in STD_LOGIC;-时钟控制； k3 : in STD_LOGIC;-时钟控制；第三个时钟高电平改变标志寄存器的值； order : in STD_LOGIC_VECTOR (15 downto 0);-命令输入； Pcin:in STD_LOGIC_VECTOR(15 downto 0);-pc输入； Rst:in STD_LOGIC;-复?； Rwb : in STD_LOGIC_VECTOR (7 downto 0);-回写数据； Rwba : in STD_LOGIC

6、;-回?丛市?高电平有效 Aluout : out STD_LOGIC_VECTOR (15 downto 0);-计算结果输出； addr : out STD_LOGIC_VECTOR (15 downto 0)-内存?刂? ); end CPU_operation;architecture Behavioral of CPU_operation is type reg is array(0 to 7) of std_logic_vector(7 downto 0); signal sreg:reg; signal F9:std_logic_vector(8 downto 0);-判断结果是

7、否进位、是否为零； signal sregflag:std_logic_vector(1 downto 0);-标志寄存器；begin process(Rwb,Rwba,k2,order,sreg,Pcin,sregflag,F9) begin if Rwba=1 then sreg(conv_integer(order(10 downto 8)=Rwb;-回写 end if; if Rst=1 then sreg(7)=00000000; sreg(6)=00000000; F9(8)-mov Ri,Im Aluout(7 downto 0)=order(7 downto 0); Aluou

8、t(15 downto 8)-LDA Ri,X addr(15 downto 8)=sreg(7); addr(7 downto 0)= order(7 downto 0); Aluout(15 downto 8)-STA Ri,X Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8); Aluout(15 downto 8)=11111111; addr(7 downto 0)=order(7 downto 0); addr(15 downto 8)-mov Ri,Rj Aluout(7 downto 0)=sreg(conv_int

9、eger(order(2 downto 0); Aluout(15 downto 8)-mov Ri,(Rj) addr(7 downto 0)=sreg(conv_integer(order(2 downto 0); addr(15 downto 8)-mov Ri,R7/R6+x addr-Adc,Ri,Im Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8)+order(7 downto 0)+sregflag(1); F9=(0&sreg(conv_integer(order(10 downto 8)+(0&order(7 d

10、ownto 0); Aluout(15 downto 8)-Adc,Ri,Rj,Ri+Rj+Cy-Ri Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8)+sreg(conv_integer(order(2 downto 0)+sregflag(1); F9=(0&sreg(conv_integer(order(10 downto 8)+(0&order(7 downto 0); Aluout(15 downto 8)-SBB Ri,Im Aluout(7 downto 0)=sreg(conv_integer(order(10 do

11、wnto 8)-order(7 downto 0)-sregflag(1); F9=(0&sreg(conv_integer(order(10 downto 8)-(0&order(7 downto 0); Aluout(15 downto 8)-SBB Ri,Rj,Ri-Rj-Cy-Ri Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8)-sreg(conv_integer(order(2 downto 0)-sregflag(1); F9=(0&sreg(conv_integer(order(10 downto 8)-(0& or

12、der(7 downto 0); Aluout(15 downto 8)-AND Ri,Im Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8) and order(7 downto 0); F9(7 downto 0)=(sreg(conv_integer(order(10 downto 8)and(order(7 downto 0); Aluout(15 downto 8)-AND Ri,Rj Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8) and sreg(conv

13、_integer(order(2 downto 0); F9(7 downto 0)=sreg(conv_integer(order(10 downto 8) and order(7 downto 0); Aluout(15 downto 8)-OR Ri,Im Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8) or order(7 downto 0); F9(7 downto 0)=(sreg(conv_integer(order(10 downto 8) or (order(7 downto 0); Aluout(15 down

14、to 8)-OR Ri,Rj Aluout(7 downto 0)=sreg(conv_integer(order(10 downto 8) or sreg(conv_integer(order(2 downto 0); F9(7 downto 0)=(sreg(conv_integer(order(10 downto 8) or (order(7 downto 0); Aluout(15 downto 8)-JMP Addr Aluout-JZ sign if sregflag(0)=1 then if order(7)=0 then Aluout= Pcin+(00000000&order

15、(7 downto 0); else Aluout = Pcin+(11111111 & order(7 downto 0); end if; else Aluout -JC sign if sregflag(1) = 1 then if order(7)=0 then Aluout= Pcin+(00000000&order(7 downto 0); else Aluout = Pcin+(11111111 & order(7 downto 0); end if; else Aluout NULL; end case; end if; end process; process(k3,F9,o

16、rder) begin if rst = 1 then sregflag(0)=0; sregflag(1) sregflag(1) = F9(8); if F9(7 downto 0) = 00000000 then sregflag(0) = 1; else sregflag(0) sregflag(0) null; end case; end if; end process;end Behavioral;存储管理模块entity CPU_Momery is Port ( k3 : in STD_LOGIC;-时钟控制； order : in STD_LOGIC_VECTOR (15 do

17、wnto 0);-命令输入； alu : in STD_LOGIC_VECTOR (15 downto 0);-计算结果输?； datain : in STD_LOGIC_VECTOR (7 downto 0);-从内存读入的?； dataout: out STD_LOGIC_VECTOR (7 downto 0);-存入内存的数； Rtmp:out STD_LOGIC_VECTOR (15 downto 0);-数据输出；送向回写模块； sta : out STD_LOGIC;-存数控制；高电平有效； lda : out STD_LOGIC);-取数控制；高电平有效?end CPU_Mome

18、ry;architecture Behavioral of CPU_Momery isbeginprocess(k3,alu,order,datain)beginif k3=1 then -高电平操作； case order(15 downto 11) is when 00001=-取数； lda=1; Rtmp(7 downto 0)-取数； lda=1; Rtmp(7 downto 0)-取数； lda=1; Rtmp(7 downto 0)-存数； sta=1; dataout Rtmp=alu;-不访存；运算结果直接送下一个模块； lda=0; sta=0; end case; els

19、e lda=0; sta=0; end if; end process;end Behavioral;访存模块entity CPU_ToMomery is Port ( sta : in STD_LOGIC;-存数指令； lda : in STD_LOGIC;-取数指令； Addr: in STD_LOGIC_VECTOR(15 downto 0);-内存地址； flag: in STD_LOGIC;-取指标志； PCaddr: in STD_LOGIC_VECTOR(15 downto 0);-指令地址输入； orderout:out STD_LOGIC_VECTOR(15 downto 0

20、);-指令输出； dataout : out STD_LOGIC_VECTOR (7 downto 0);-从内存中取出的数； datain : in STD_LOGIC_VECTOR (7 downto 0);-需要存入内存的数; ABUS : out STD_LOGIC_VECTOR(15 downto 0);-地址总线? DBUS : inout STD_LOGIC_VECTOR(15 downto 0);-数据总线； CS: out STD_LOGIC;-片选信号；低电平有效； RD: out STD_LOGIC;-读信号；低电平有效； WR: OUT STD_LOGIC; -写信号；

21、低电平有? nBHE:out std_logic; nBLE:out std_logic ); end CPU_ToMomery;architecture Behavioral of CPU_ToMomery isbeginprocess(sta,lda,datain,DBUS,flag) begin if flag=1 then -取指令； CS=0; RD=0; WR=1; nBHE=0; nBLE=0; ABUS=PCaddr; orderout=DBUS; DBUS=ZZZZZZZZZZZZZZZZ; elsif sta=1 then -存数访存； CS=0; RD=1; WR=0;

22、nBHE=0; nBLE=0; ABUS=Addr; DBUS(7 downto 0)=datain; DBUS(15 downto 8)=11111111; elsif lda=1 then -取数访存； CS=0; RD=0; WR=1; nBHE=0; nBLE=0; ABUS=Addr; dataout=DBUS(7 downto 0); DBUS=ZZZZZZZZZZZZZZZZ; else CS=1; RD=1; WR=1; nBHE=1; nBLE=1; DBUS-mov Ri,Im Pcbacka=1; Pcback=Pcin+1; dataA=1; dataout-LDA Pcbacka=1; Pcback=Pcin+1; dataA=1; dataout-STA Pcbacka=1; Pcback=Pcin+1; dataA-mov Ri,Rj Pcbacka=1; Pcback=Pcin+1; dataA=1; dataout=datain(7 downto 0); when