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本文(电气工程及其自动化专业AT89S52单片机应用大学毕业论文英文文献翻译及原文.docx)为本站会员(b****1)主动上传,冰豆网仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知冰豆网(发送邮件至service@bdocx.com或直接QQ联系客服),我们立即给予删除!

电气工程及其自动化专业AT89S52单片机应用大学毕业论文英文文献翻译及原文.docx

1、电气工程及其自动化专业AT89S52单片机应用大学毕业论文英文文献翻译及原文毕 业 设 计(论文)外 文 文 献 翻 译文献、资料中文题目:AT89S52单片机应用文献、资料英文题目: AT89S52 MCU Applications文献、资料来源:文献、资料发表(出版)日期:院 (部): 专 业: 电气工程及其自动化班 级: 姓 名: 学 号: 指导教师: 翻译日期: 2017.02.14本科毕业设计(论文)AT89S52单片机应用中英文翻译专业名称: 电气工程及其自动化 年级班级: 学生姓名: 指导老师: AT89S52 MCU ApplicationsFunction Character

2、istic DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pi

3、nout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexi

4、ble and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex

5、serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sy

6、stem to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin DescriptionVCC :Supply voltage.GND :Ground.Port 0:Port 0 is an 8-bit open drain bidirectional I/O port. As an output

7、 port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Po

8、rt 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1:Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL i

9、nputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/co

10、unter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.Table 1 The second function of the P1 portPort PinAlternate Functions

11、P1.0T2 (external count input to Timer/Counter 2), clock-outP1.1T2EX (Timer/Counter 2 capture/reload trigger and direction control)P1.5MOSI (used for In-System Programming)P1.6MISO (used for In-System Programming)P1.7SCK (used for In-System Programming)Port 2:Port 2 is an 8-bit bidirectional I/O port

12、 with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the inter

13、nal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory t

14、hat use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 o

15、utput buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control sig

16、nals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.Table 2 The second function of the P3 portPort PinAlternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2 (external interrupt 0)P3.3 (external interrupt 1)P3.4T0 (timer 0 external

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