eda程序.docx

1、eda程序library ieee; -秒计时器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity second is port(rst,clk:in std_logic; sectomun:out std_logic; secge:out std_logic_vector(3 downto 0); secshi: std_logic_vector(3 downto 0);end second;architecture one of second is begin process(rst,clk)variab

2、le sec1: std_logic_vector(3 downto 0);variable sec2: std_logic_vector(3 downto 0);begin if rst=1 then sec1:=”0000”;sec2:=”0000”;elsif clkevent and clk=1 then if sec1=”0000” then sec1:=”0000”; else sec2:=sec2+1;end if; else sec1:=sec1+1; end if;if sec1=”1001” and sec2=”0101” then sectomun=1; else sec

3、tomun=0; end if;end if;end process;secge=sec1;secshi=sec2;end;library ieee; -分计时器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity minute is port(rst:in std_logic; sectomun:in std_logic; muntohour:out std_logic; munge:out integer range 0 to 9; munshi: out integer range 0 to 5);end

4、 minute;architecture one of minute is begin process(rst,sectomun)variable mun1:integer range 0 to 9;variable mun2:integer range 0 to 5;begin if rst=1 then mun1:=0;mun2:=0;elsif sectomunevent and sectomun=1 then mun1:=mun1+1; if mun1=10 then mun1:=0; mun2:=mun2+1;end if; if mun2=6 then mun2:=0; munto

5、hour=1; else muntohour=0; end if;end if;munge=mun1;munshi=mun2;end process;end;library ieee; -小时计时器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hour is port(rst:in std_logic; muntohour:in std_logic; hourge:out integer range 0 to 9; hourshi: out integer range 0 to 2);end hour;

6、architecture one of hour is begin process(rst,muntohour)variable hour1:integer range 0 to 9;variable hour2:integer range 0 to 2;begin if rst=1 then hour1:=0;hour2:=0;elsif muntohourevent and muntohour=1 then hour1:=hour1+1; if hour1=10 then hour1:=0; hour2:=hour2+1; end if;if hour1=4 and hour2=2 the

7、n hour1:=0;hour2:=0; end if;end if;hourge=hour1;hourshi=hour2;end process;end;library ieee; -设置时钟use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity settime is port(s1,s0:in std_logic; hourge,munge:buffer integer range 0 to 9; hourshi:buffer integer range 0 to 2; munshi:buffer integ

8、er range 0 to 5);end entity settime;architecture one of settime issignal sets:std_logic_vector(1 downto 0);beginsetshourshi=hn2;hourgemunshi=min2;mungehourshi=hn2;hourge=hn1;munshi=min2;mungenull;end case;end process;end;library ieee;-7段译码器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all

9、; entity led_7 is port(ain:in integer range 0 to 9; led7s:out std_logic_vector(0 to 6); end entity led_7; architecture behav of led_7 isbegin process(ain) begin case ain is when 0=led7sled7sled7sled7sled7sled7sled7sled7sled7sled7sled7s=0000000; end case;end process;end behav;library IEEE; -分频计use IE

10、EE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity fenpin is port (rst,clk : in STD_LOGIC; pin: out STD_LOGIC);end fenpin;architecture a of fenpin is signal count: integer range 0 to 4; signal t:std_logic;begin process (rst,clk) begin if rst=1 then count=0; els

11、if clkevent and clk=1 then count= count + 1 ;t=t; if count=4 then count=0;t=not t; end if ; end if; pin=t; end process;end a;library ieee; -闹钟use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alarm is port(pin,muntohour:in std_logic; alarm:out std_logic );end entity alarm;architec

12、ture one of alarm isbeginprocess(muntohour,pin)beginif muntohour=1 then alarm=pin;else alarmCLKK,rst=RET_T,sectomun=SECCO, secge=SEC_1,secshi=SEC_2);U2:minute port map(rst=RET_T,muntohour=MINCO,sectomun=SECCO, munge=MIN_1,munshi=MIN_2);U3:hour port map(rst=RET_T,muntohour=MINCO,hourge=HOUR_1,hourshi

13、=HOUR_2);U4:settime port map(s1=S1,s0=S0,secge=SEC_1,secshi=SEC_2, munge=MIN_1,munshi=MIN_2,hourge=HOUR_1,hourshi=HOUR_2);U5:fenpin port map(clk=CLKK,rst=RET_T,pin=PIN);U6:alarm port map(pin=PIN,muntohour=MINCO,alarm=ALARM1);U7:led_7 port map(ain=SEC_1,ain=SEC_2,ain=MIN_1,ain=MIN_2,ain=HOUR_1,ain=HO

14、UR_2);END one;library ieee; -秒计时器use ieee.std_logic_1164.all;use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity second is port(rst,clk:in std_logic; sectomun:out std_logic; secge:out std_logic_vector( 0 to 3); secshi: out std_logic_vector( 0 to 3);end second;architecture one of se

15、cond is begin process(rst,clk)variable sec1:std_logic_vector( 0 to 3);variable sec2:std_logic_vector( 0 to 2);begin if rst=1 then sec1:=0000;sec2:=0000;elsif clkevent and clk=1 then sec1:=sec1+1; if sec1=1010 then sec1:=0000; sec2:=sec2+1;end if; if sec2=110 then sec2:=0000; end if; if sec1=0000 and

16、 sec2=1010 then sectomun=1; else sectomun=0; end if;end if;secge=sec1;secshi=sec2;end process;end;library ieee; -分计时器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity minute is port(rst:in std_logic; sectomun:in std_logic; muntohour:out std_logic; munge:out std_logic_vector( 0 to

17、3); munshi: out std_logic_vector( 0 to 3);end entity;architecture one of minute is beginprocess(rst,sectomun)variable mun1:std_logic_vector( 0 to 3);variable mun2:std_logic_vector( 0 to 3);begin if rst=1 then mun1:=0;mun2:=0;elsif sectomunevent and sectomun=1 then mun1:=mun1+1; if mun1=10 then mun1:

18、=0; mun2:=mun2+1;end if; if mun2=6 then mun2:=0; muntohour=1; else muntohour=0; end if;end if;munge=mun1;munshi=mun2;end process;end;library ieee; -小时计时器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hour is port(rst:in std_logic; muntohour:in std_logic; hourge:out std_logic_ve

19、ctor( 0 to 3); hourshi: out std_logic_vector( 0 to 2);end hour;architecture one of hour is begin process(rst,muntohour)variable hour1:std_logic_vector( 0 to 3);variable hour2:std_logic_vector( 0 to 2);begin if rst=1 then hour1:=0;hour2:=0;elsif muntohourevent and muntohour=1 then hour1:=hour1+1; if

20、hour1=10 then hour1:=0; hour2:=hour2+1; end if;if hour1=4 and hour2=2 then hour1:=0;hour2:=0; end if;end if;hourge=hour1;hourshi=hour2;end process;end;library ieee; -设置时钟use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity settime is port(s1,s0:in std_logic; hourge,munge:buffer std_l

21、ogic_vector( 0 to 3); hourshi:buffer std_logic_vector( 0 to 2); munshi:buffer std_logic_vector( 0 to 3);end entity settime;architecture one of settime issignal sets:std_logic_vector(1 downto 0);beginsetshourshi=hn2;hourgemunshi=min2;mungehourshi=hn2;hourge=hn1;munshi=min2;mungenull;end case;end proc

22、ess;end;library ieee;-7段译码器use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity led_7 is port(ain:in std_logic_vector( 0 to 3); led7s:out std_logic_vector(0 to 6); end entity led_7; architecture behav of led_7 isbegin process(ain) begin case ain is when 0=led7sled7sled7sled7sled7sled7sled7sled7sled7sled7sled7s=0000000; end case;end process;end behav;library IEEE; -分频计use