verilog编写的基本电路逻辑与仿真.docx

1、verilog编写的基本电路逻辑与仿真集成电路与Verilog语言 实验1：分别用门级建模、数据流级建模、和行为级建模实现一个2选1的MUX，两个输入端分别为A和B，当选择端SEL=0时，输出F选择A；当选择端SEL=1时，输出F选择B。门级建模：源代码：/MUX2to1 gatelevelmodule MUX_gate(a,b,sel,f); input a; input b; input sel; output f; reg f;wire nsel,y1,y2;not unot(nsel,sel);and u1and(y1,a,nsel);and u2and(y2,b,sel);or uo

2、r(f,y1,y2);endmodule综合结果：TB代码：module tb_MUX_gate; / Inputs reg a; reg b; reg sel; / Outputs wire f; / Instantiate the Unit Under Test (UUT) MUX_gate uut ( .a(a), .b(b), .sel(sel), .f(f) ); initial begin / Initialize Inputs a = 0; b = 0; sel = 0; / Wait 100 ns for global reset to finish #10 / Add sti

3、mulus here a=1; b=0; sel=0; #10; a=1; b=0; sel=1; #10; #10$finish; endendmodule仿真结果：数据流级建模：源代码：/MUX2to1 datapromodule MUX_datapro(a,b,sel,f); input a; input b; input sel; output f;reg f;wire nsel,y1,y2;assign nsel=sel;assign y1=a&nsel;assign y2=b&sel;assign f=y1|y2; endmodule综合结果：TB代码：module tb_MUX_

4、datarpro; / Inputs reg a; reg b; reg sel; / Outputs wire f; / Instantiate the Unit Under Test (UUT) MUX_datapro uut ( .a(a), .b(b), .sel(sel), .f(f) ); initial begin / Initialize Inputs a = 0; b = 0; sel = 0; / Wait 100 ns for global reset to finish #10; / Add stimulus here a=1; b=0; sel=0; #10; a=1

5、; b=0; sel=1; #10; #10$finish; enendmodule仿真结果：行为级建模：源代码：/MUX2to1 behavmodule MUX_behav(f,a,b,sel);input a,b,sel;output f;reg f;reg y1,y2,nsel;always (a or b or sel)begin nsel =sel; y1 = a&nsel; y2 = b&sel; f = y1|y2; endendmodule综合结果：TB代码：module tb_MUX_behav; / Inputs reg a; reg b; reg sel; / Outpu

6、ts wire f; / Instantiate the Unit Under Test (UUT) MUX_behav uut ( .a(a), .b(b), .sel(sel), .f(f) ); initial begin / Initialize Inputs a = 0; b = 0; sel = 0; / Wait 100 ns for global reset to finish #10; / Add stimulus here a=1; b=0; sel=0; #10; a=1; b=0; sel=1; #10; #10$finish; end endmodule仿真结果：实验

7、2题目：实现一个计数器，计数时计数器可从0计到10。源代码：module counter(din,up1_down0,clk,nrst,sta1_pau0,load,counter); input3:0 din; input up1_down0; input clk; input nrst; input sta1_pau0; input load; output 3:0 counter; reg 3:0 counter; always (posedge clk or negedge nrst)begin if(nrst) counter = 4b0000; else if(load) coun

8、ter = din; else begin if(sta1_pau0) counter = counter; else if(up1_down0) if (counter = 10) counter = 4b0000; else counter = counter + 1; else if (counter = 0) counter = 4b1010; else counter = counter - 1; end endendmodule综合结果：TB代码：module tb2; / Inputs reg 3:0 din; reg up1_down0; reg clk; reg nrst;

9、reg sta1_pau0; reg load; / Outputs wire 3:0 counter; / Instantiate the Unit Under Test (UUT) counter uut ( .din(din), .up1_down0(up1_down0), .clk(clk), .nrst(nrst), .sta1_pau0(sta1_pau0), .load(load), .counter(counter) ); initial clk = 1b0; always #5 clk = clk; initial begin / Initialize Inputs din

10、= 0; up1_down0 = 0; nrst = 0; sta1_pau0 = 0; load = 0; / Wait 100 ns for global reset to finish #50; / Add stimulus here /从0开始加计数 din = 4b0111; nrst = 1; up1_down0 = 1; sta1_pau0 = 1; #210; /暂停 sta1_pau0 = 0; #20; /从7开始减计数 load = 1; #10; load = 0; sta1_pau0 = 1; up1_down0 = 0; #200; #20 $finish; end

11、 endmodule仿真结果：实验3题目：由Morre状态机设计一个简单的交通灯，假定红灯时间为9个时间单位，绿灯时间为6个时间单位，黄灯时间为3个时间单位。源代码：module light_machine(clk,nrst,y,t); input clk; input nrst; output 1:0 y; output 3:0 t; reg 3:0 q; reg 1:0 y; reg 1:0 state; reg 3:0 t; parameter green = 2b00,yellow = 2b01,red = 2b11;initial begin q = 4b0; t = 4b0;end

12、always (posedge clk or negedge nrst)begin if(!nrst) begin state = green; y = 2bz; end else case(state) green: begin q = q +1; t = q; if(q = 5) begin q = 4b0; state = yellow; end else begin y = 2b00; state = green; end end yellow: begin q = q +1; t = q; if (q = 2) begin q = 4b0; state = red; end else

13、 begin y = 2b01; state = yellow; end end red: begin q = q + 1; t = q; if (q = 8) begin q = 4b0; state = green; end else begin y = 2b11; state = red; end end endcaseendendmodule综合结果：TB代码：module tb_2; / Inputs reg clk; reg nrst; / Outputs wire 1:0 y; wire 3:0 t; / Instantiate the Unit Under Test (UUT)

14、 light_machine uut ( .clk(clk), .nrst(nrst), .y(y), .t(t) ); initial clk = 1b0; always #5 clk = clk; initial begin / Initialize Inputs nrst = 0; / Wait 100 ns for global reset to finish #30; / Add stimulus here nrst = 1; #500; #20$finish; end endmodule仿真结果：实验4题目：对一个400MHz的时钟分别完成2、4、8分频。源代码：module di

15、vclk(clkin,nrst,din, clkout); input clkin; input nrst; input 1:0 din; output clkout; reg 28:0 q; reg clkout; initialbegin q =29b0;end always (posedge clkin or negedge nrst)begin if(nrst) q = 29b0; else q = q + 29b1; endalways (posedge clkin)begin case(din) 2b00: clkout = q0; 2b01: clkout = q1; 2b10:

16、 clkout = q2; default: clkout = 1bz; endcaseendendmodule综合结果：TB文件：module tb_div; / Inputs reg clkin; reg nrst; reg 1:0 din; / Outputs wire clkout; / Instantiate the Unit Under Test (UUT) divclk uut ( .clkin(clkin), .nrst(nrst), .din(din), .clkout(clkout) ); initial clkin = 1b0; always #1.25 clkin =

17、clkin; initial begin / Initialize Inputs nrst = 0; din = 2b11; / Wait 100 ns for global reset to finish #50; / Add stimulus here nrst = 1; din = 2b00; #50; din = 2b01; #50; din = 2b10; #50; din = 2b11; #50; #20$finish; end endmodule仿真结果：实验5题目：按照病情严重程度将8名病人分配到8个病房，1号病房病情最轻，8号病房病人病情最严重。每个病房有一个按钮用于呼叫医生

18、，在医生办公室有个显示屏，用于显示哪个病房按了按钮。由于病情不同，要求当病情较严重的病房按了按钮后，医生办公室的显示屏要优先显示其病房号。源代码：module priority_encoder(clk,I0,I1,I2,I3,I4,I5,I6,I7,Y); input clk; input I0; input I1; input I2; input I3; input I4; input I5; input I6; input I7; output 2:0 Y; reg 2:0 Y;always (posedge clk )begin if(I7) Y = 3b111; else if(I6)

19、 Y = 3b110; else if(I5) Y = 3b101; else if(I4) Y = 3b100; else if(I3) Y = 3b011; else if(I2) Y = 3b010; else if(I1) Y = 3b001; else if(I0) Y = 3b000; else Y = 3bz; endendmodule综合结果：TB文件：module tb2; / Inputs reg clk; reg I0; reg I1; reg I2; reg I3; reg I4; reg I5; reg I6; reg I7; / Outputs wire 2:0 Y

20、; / Instantiate the Unit Under Test (UUT) priority_encoder uut ( .clk(clk), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5), .I6(I6), .I7(I7), .Y(Y) ); initial clk = 1b0; always #2 clk = clk; initial begin / Initialize Inputs I0 = 0; I1 = 0; I2 = 0; I3 = 0; I4 = 0; I5 = 0; I6 = 0; I7 = 0; / Wait 100 ns for global reset to finish #10; / Add stimulus here I7,I6,I5,I4,I3,I2,I1,I0 = 8b1110_1101; #10; I7,I6,I5,I4,I3,I2,I1,I0 = 8b0110_1011; #10; I7,I6,I5,I4,I3,I2,I1,I0 = 8b0011_0110; #10; 仿真结果：