信息自动化专业外文翻译.docx

1、信息自动化专业外文翻译外文资料原文 Transmitting and receiving serial data The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destina

2、tion, a second UART re-assembles the bits into complete bytes.Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert the transmitted information between its seque

3、ntial and parallel form at each end of the link. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. The UART usually does not directly generate or receive the external signals used between different items of equipment. Typically, sepa

4、rate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels.External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically, the presence or absence of c

5、urrent (in current loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wir

6、es). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC-LIN for power line communication. Communication may be full duplex (both send and receive at the same time) or half duplex (devices take turns transmitting and receiving). As of 2008, UAR

7、Ts are commonly used with RS-232 for embedded systems communications. It is useful to communicate between microcontrollers and also with PCs. Many chips provide UART functionality in silicon, and low-cost chips exist to convert logic level signals (such as TTL voltages) to RS-232 level signals (for

8、example, Maxims MAX232). Asynchronous receive and transmit In asynchronous transmitting, teletype-style UARTs send a start bit, five to eight data bits, least-significant-bit first, an optional parity bit, and then one, one and a half, or two stop bits. The start bit is the opposite polarity of the

9、data-lines idle state. The stop bit is the data-lines idle state, and provides a delay before the next character can start. (This is called asynchronous start-stop transmission). In mechanical teletypes, the stop bit was often stretched to two bit times to give the mechanism more time to finish prin

10、ting a character. A stretched stop bit also helps resynchronization. The parity bit can either make the number of one bits between any start/stop pair odd, or even, or it can be omitted. Odd parity is more reliable because it assures that there will always be at least one data transition, and this p

11、ermits many UARTs to resynchronize. In synchronous transmission, the clock data is recovered separately from the data stream and no start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. An as

12、ynchronous transmission sends no characters over the interconnection when the transmitting device has nothing to send - only idle stop bits; but a synchronous interface must send pad characters to maintain synchronism between the receiver and transmitter. The usual filler is the ASCII SYN character.

13、 This may be done automatically by the transmitting device. USART chips have both synchronous and asynchronous modes. Serial to Parallel Algorithm Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receive

14、r must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units. When a word is given to the UART for Asynchronous transmissions, a bit called the Start Bit is added to the beginning of each word that is to be transmi

15、tted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission

16、of the remaining bits in the word. (This requirement was set in the days of mechanical teleprinters and is easily met by modern electronic equipment.) After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmi

17、ssion is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will exa

18、mine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on. The sender does not know when the receiver has “looked” at the value of the bit. The sender only knows when the clock says to begin trans

19、mitting the next bit of the word.When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter. When the receiver has rec

20、eived all of the bits in the data word, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled a

21、nd will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted. Regardless of whether the data was received correctly or not, the UART au

22、tomatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host. If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent. Becau

23、se asynchronous data is “self synchronizing”, if there is no data to transmit, the transmission line can be idle. A data communication pulse can only be in one of two states but there are many names for the two states. When on, circuit closed, low voltage, current flowing, or a logical zero, the pul

24、se is said to be in the space condition. When off, circuit open, high voltage, current stopped, or a logical one, the pulse is said to be in the mark condition. A character code begins with the data communication circuit in the space condition. If the mark condition appears, a logical one is recorde

25、d otherwise a logical zero.Figure 1 shows this format. The start bit is always a 0 (logic low), which is also called a space. The start bit signals the receiving DTE that a character code is coming. The next five to eight bits, depending on the code set employed, represent the character. In the ASCI

26、I code set the eighth data bit may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., 1) condition and called the stop bit(s). They provide a rest interval for the receiving DTE so that it may prepare for the next character which may be after the stop bit(s). The res

27、t interval was required by mechanical Teletypes which used a motor driven camshaft to decode each character. At the end of each character the motor needed time to strike the character bail (print the character) and reset the camshaft. All operations of the UART hardware are controlled by a clock sig

28、nal which runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid a

29、nd signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) h

30、ave elapsed, the contents of the shift register is made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. In some common types

31、 of UART, a small first-in, first-out (FIFO) buffer memory is inserted between the receiver shift register and the host system interface. This allows the host processor more time to handle an interrupt from the UART and prevents loss of received data at high rates. Transmission operation is simpler

32、since it is under the control of the transmitting system. As soon as data is deposited in the shift register, the UART hardware generates a start bit, shifts the required number of data bits out to the line,generates and appends the parity bit (if used), and appends the stop bits. Since transmission

33、 of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since full-duplex operation requi