微电子课程设计.docx

1、微电子课程设计1. 流水灯实验2. 出租车计价器3. 交通灯实验4. 乘法器实验1. module top(clk,t,out); output wire0:2 out; input clk; input 1:0t; wire outclk; div #1000 mydiff(outclk,t,clk); jishu myjishu(out,outclk);endmodulemodule div(outclk,t,clk); output reg outclk; input 1:0 t; input clk; parameter count=1000; integer n=0,m=0; ini

2、tial outclk=1; always(t) case(t) 2b00:m=count; 2b01:m=2*count; 2b10:m=3*count; 2b11:m=4*count; default:m=count; endcase always(edge clk) begin if(nm)n=n+1; else if(n=m) begin outclk=outclk; n=0; end endendmodule module jishu(out,clk); output reg2:0 out; input clk; integer q=0; always(posedge clk) be

3、gin q=q+1; case(q) 1:out=3b100; 2:out=3b010; 3:out=3b001; 4:out=3b110; 5:out=3b011; 6:out=3b101; 7:out=3b111; 8: begin out=3b000; q=0; end default:q=0; endcase endendmodule2.module top(start,pause,stop,clk,display); output 14:0display; input start,stop,pause,clk; wire clkd,clkt; wire 13:0out; wire 1

4、3:0outp; wire15:0 money; wire15:0 distance; wire p_s; assign p_s=pause; div #1000 mydiv1(clkd,clk,stop); div #1000 mydiv2(clkt,clk,p_s); jifei myjifeei(out,outp,start,stop,pause,clkd,clkt); bcd mybcd(out,money); bcd mybcd2(outp,distance); dongtai mydongtai(display,distance,money,clk);endmodulemodule

5、 jifei(out,outp,restart,stop,pause,clkd,clkt); output reg0:13 out; output reg0:13 outp; input clkd,clkt; input restart,stop,pause; integer p=0,t=0; always(restart,posedge clkd) begin if(!pause)&(!stop) begin p=p+1; if(p5) out=out+140; if(p5&out5000) out=out+70; end if(restart=1) begin p=0; out=14b00

6、00_0000_0000_00; end outp=p; end always(posedge clkt) /begin /if(pause) begin t=t+1; if(t=3) begin out=out+50; t=0; end end /end endmodulemodule div(oclk,clk,rst); output reg oclk; input clk,rst; integer p=0; parameter COUNT=1000; initial oclk=1b1; always(edge clk) begin if(!rst) begin p=p+1; if(p=C

7、OUNT) begin oclk=oclk; p=0; end end else p=0; endendmodulemodule bcd(in,out); input 13:0in; output 15:0out; reg 13:0bin; reg 15:0result; always(in) begin result=16b0; bin=in; repeat(13) begin result0=bin13; if(result3:04) result3:0=result3:0+4d3; if(result7:44) result7:4=result7:4+4d3; if(result11:8

8、4) result11:8=result11:8+4d3; if(result15:124) result15:12=result15:12+4d3; result=result1; bin=bin1; end result0=bin13; end assign out=result; endmodule/*.*# module dongtai(out,ind16,inm16,clk); output 14:0out; input 15:0ind16; input 15:0inm16; input clk; reg 14:0ott; reg 3:0inn; integer i=1; initi

9、al ott=13b1; always(ind16,inm16,posedge clk) begin case(i) 1:begin inn=inm1615:12; ott14:8=7b1000_000; end 2:begin inn=inm1611:8; ott14:8=7b0100_000; end 3:begin inn=4b1111; ott14:8=7b0010_000; end 4:begin inn=inm167:4; ott14:8=7b0001_000; end 5:begin inn=inm163:0; ott14:8=7b0000_100; end 6:begin in

10、n=ind167:4; ott14:8=7b0000_010; end 7:begin inn=ind163:0; ott14:8=7b0000_001; i=0; end endcase case(inn) 4b0000 : ott7:0=8b11111100; /0 4b0001 : ott7:0=8b01100000; /1 4b0010 : ott7:0=8b11011010; /2 4b0011 : ott7:0=8b11110010; /3 4b0100 : ott7:0=8b01100110; /4 4b0101 : ott7:0=8b10110110; /5 4b0110 :

11、ott7:0=8b10111110; /6 4b0111 : ott7:0=8b11100000; /7 4b1000 : ott7:0=8b11111110; /8 4b1001 : ott7:0=8b11110110; /9 4b1111 : ott7:0=8b00000001; /. default: ott=8b1111_1111; endcase i=i+1; end assign out=ott; endmodule 3. module jtd(z,g,c,clk,reset); output reg 2:0 z,g; input c; input clk; input reset

12、; reg e,f,s; integer countg=0,countz=0; always(posedge clk) begin if(reset=1) begin z=3b001;g=3b100;countz=0;countg=0; end else begin if(c=0) begin z=3b001; g=3b100; countg=0; if(countz16) countz=countz+1; end else begin if(z!=3b100) begin if(countz16) countz=countz+1; else if(countz19) begin g=3b10

13、0; countg=0; z=3b001; end else if(countg15) begin g=3b010; countg=countg+1; end else countg=countg+1; end end end endendmodule 4.module top(in1,in2,outd,restart,clk); input restart; input 7:0 in1,in2; input clk; output 12:0outd; wire 19:0outbcd; wire15:0binary; mul mymul(in1,in2,binary,restart); bcd

14、 mybcd(binary,outbcd); dongtai mydongtai(outd,outbcd,clk);endmodulemodule mul(in1,in2,out,restart); output 15:0 out; input 7:0in1; input 7:0in2; input restart; reg 15:0add; always(in1,in2,restart) begin if(restart=1) add=16b0; else begin if(in20=1) add=8b0,in17:0; else add=16b0; if(in21=1) add=add+7

15、b0,in17:0,1b0; if(in22=1) add=add+6b0,in17:0,2b0; if(in23=1) add=add+5b0,in17:0,3b0; if(in24=1) add=add+4b0,in17:0,4b0; if(in25=1) add=add+3b0,in17:0,5b0; if(in26=1) add=add+2b0,in17:0,6b0; if(in27=1) add=add+1b0,in17:0,7b0; end end assign out=add; endmodule module bcd(binary,bcd); input 15:0binary;

16、 output 19:0 bcd; reg15:0 bin; reg19:0 result; always(binary) begin result=20b0; bin=binary; repeat(15) begin result0=bin15; if(result3:04) result3:0=result3:0+4d3; if(result7:44) result7:4=result7:4+4d3; if(result11:84) result11:8=result11:8+4d3; if(result15:124) result15:12=result15:12+4d3; if(res

17、ult19:164) result19:16=result19:16+4d3; result=result1; bin=bin1; end result0=bin15; end assign bcd=result; endmodule module dongtai(outd,in20,clk); output 12:0outd; input 19:0in20; input clk; reg 12:0ott; reg 3:0inn; integer i=1; initial ott=13b1; always(in20,posedge clk) begin case(i) 1:begin inn=

18、in2019:16; ott12:8=5b10000; end 2:begin inn=in2015:12; ott12:8=5b01000; end 3:begin inn=in2011:8; ott12:8=5b00100; end 4:begin inn=in207:4; ott12:8=5b00010; end 5:begin inn=in203:0; ott12:8=5b00001; i=0; end endcase i=i+1; case(inn) 4b0000 : ott7:0=8b11111100; /0 4b0001 : ott7:0=8b01100000; /1 4b001

19、0 : ott7:0=8b11011010; /2 4b0011 : ott7:0=8b11110010; /3 4b0100 : ott7:0=8b01100110; /4 4b0101 : ott7:0=8b10110110; /5 4b0110 : ott7:0=8b10111110; /6 4b0111 : ott7:0=8b11100000; /7 4b1000 : ott7:0=8b11111110; /8 4b1001 : ott7:0=8b11110110; /9 default: ott=8b1111_1111; endcase end assign outd=ott; endmodule