基于锁相环的测量信号的处理与仿真Word格式文档下载.docx

1、Frequency Modulation in Microwave Phase Lock Loop SynthesizersAbstract This paper shows, that frequency modulation bandwidth of phase locked controlled oscillator （CO） can be simple expanded using precorrecting circuit （corrector） connected to control port of oscillator. A method is presented of cal

2、culation of corrector according to exact PLL and frequency response of modulation channel, with experimental demonstration presented of adequacy of described technique being shown. Index Terms Microwave PLL synthesizer, frequency modulation, maximum deviation, modulation bandwidth. I. INTRODUCTIONIn

3、 many microwave systems the synthesizer must generate frequency modulated signal in addition to monochromatic signal generation, its main function. Solution of this problem in case of phase lock loop （PLL） synthesizer becomes complicated due resistance of PLL to the CO modulation, as an automatic co

4、ntrol system. The most difficulty is the expansion of modulation band and the modulation index range. The purpose of this paper is contribution in solution of these problems. II. TARGET SETTINGIt is well known that frequency modulation possibility of phase locked CO is limited by cutoff band. Modula

5、tion bandwidth corner is equal to PLL angular frequency 1. In band above cutoff the loop makes no resistance to the CO modulation, but below cutoff its resistance increases when modulating frequency decreases. Thus, modulation bandwidth of CO must be widened up to down the PLL angular frequency. It

6、can be made by three issues: By decrease of PLL cutoff frequency; by impact modulating signal into PLL: modulation of the reference frequency, manipulation of feedback division ratio, addition of the modulating signal to control signal of phase detector;by application of linear precorrection to modu

7、lating signal for compensation of high-pass properties of PLL 2,3. Further the last method is considered. It is more effective as it makes no worse on dynamic and spectral purity characteristics of PLL synthesizer like first method and has no limitation of modulation bandwidth above like second way.

8、 III. MATHEMATICAL DESCRIPTION OF CORRECTOR MODELTo improve the modulation sensitivity of CO an active corrector instead the passive corrector 2 is proposed in Fig. 1. Fig. 1. Corrector schematicModulating signal comes to input 1. PLL control signal comes to input 2. Driving signal for CO goes out t

9、hrough output 3. A. Small signal model Corrector transfer function K1（p） from input 1 to output 3 is represented by:where a, c are gain factors of third stage at low and high frequencies respectively; is high frequency time constant of third stage; k is depth of dip of response curve in PLL corner f

10、requency area; b is gain factor of first stage at high frequencies; 1, 2 are low and high frequency time constants of dip of response curve respectively. Parameters in （1） can be selected in case of an exact PLL and modulation channel requirements. B. Large signal model Maximum deviation Fmax is lim

11、ited by several factors, which are bound with nonlinear distortions of modulated signal envelope. These distortions appear in such cases as:-voltage or current operational amplifier （opamp） saturation;-CO frequency obtain the corner of regulation curve;-appearance of dynamic distortion of opamp. In

12、first case the maximum deviation with voltage saturation is:where Usat is the saturation voltage of opamp; Kv is CO tuning sensitivity; KL（p） is closed PLL transfer function. In second case maximum deviation is constant equal to distance between average CO frequency and nearest corner of CO regulati

13、on curve. In third case maximum deviation is represented by 4 where S is slew rate of opamp. IV. CORRECTOR DESIGN AND TESTFig. 2 shows the calculated and experimental frequency responses of modulation channel with and without corrector. PLL cutoff frequency is 100 kHz, phase margin 45, CO tuning sen

14、sitivity 95 MHz/V. CO lag is not allowed. Fig. 2. Frequency responses of modulation channel normalized to CO tuning sensitivity Fig. 3 shows calculated and experimental frequency responses of maximum deviation for all types of distortions: solid curve for first, dotted curve for second and chain lin

15、e for third. Calculation was made for opamp AD829 with Usat=12V. Distance between average CO frequency and nearest corner of CO regulation curve is 50 MHz. From Fig. 2 and 3 is seen that modulation cannel bandwidth with corrector at maximum deviation 100 kHz is of 1,5 kHz facing 100 kHz without corr

16、ector. Dynamic distortions in opamp dont appear in comparison with two other types. In the fig. 2 experimental curve is close to calculated one. In Fig. 3 experimental curve differs from calculated one because current saturation of opamp has been appeared. V. CONCLUSIONSApplying an introduced correc

17、tor in PLL synthesizer one can expand the modulation bandwidth considerably. Here the simple schematic solution and low-cost elements can be used. A calculation method is simple and unlike described one in 3 incorporates the calculation of maximum frequency deviation. Fig. 3. Maximum deviation frequ

18、ency responses作者：Andrew V. Gorevoy国籍：Russia出处：Siberian Conference on Control and Communications SIBCON2009微波锁相环合成器的频率调制摘要：本论文表明，通过使用连接预先校正的电路来控制振荡器的端口，柏锁可控制振荡器的调频宽带就能够很容易被扩展。根据精确的锁相回路和录放幅频响应的调制通道，校正者提出了一种计算方法，同时提出充足的所示被描述技术的实验性说明。索引词：微波锁相回路合成器，调频，最大偏差，调制带宽.介绍在许多微波系统中，合成器必须产生调频信号，不仅仅是产生单频信号这一主要功能。由于阻

19、止锁相回路转到调制可控振荡器是一个自动控制系统，因此解决此情况下的锁相环合成器这一问题就变得复杂了。而最大的困难是调制带宽和调制索引范围的扩展。因此，本文的目的在于解决这些问题。.设定目标相位可控振荡器的调频可能性是由截止波段所限制，这是人所共知的。调制带宽角等于锁相环角频率。在截止以上的波段，这个回路对可控振荡器的调制不作任何抵抗。但低于它的波段，调制频率降低时，阻力就会增加。因此，振荡器的调制带宽必须扩大到能够降低锁相环的角频率。它可以通过三个方法解决：通过降低锁相环截止频率；冲撞调制信号进入锁相回路：调节相关频率，控制回应分割比率，除了调制信号来控制相位检测器；应用信号调制的线性预先校正

20、来补偿高通的锁相环属性。进一步考虑最后一种方法。它更有效是因为它像第一种方法一样，没有使锁相环合成器的动力特性和光谱纯度特性变得更糟糕，而且如第二种方法一样，对调制宽带没有限制。.校正模型的精确描述为了改进振荡器的调制灵敏度，使它从被动相关器成为主动相关器，如图1所示：图1 校正示意图调制信号进入输入端1，锁相环控制信号进入输入端2，振荡器的驱动信号通过输出端3出去。A 小信号模型从输入端1到输出端3的校正传递函数K1（P）的代表方式是：其中是各自低频和高频中第三级的增益因子，是第三阶段的高频时间常数，是在锁相环角频率区域的响应曲线浸深度，为在高频率第一阶段的增益因素，分别是低频和高频浸响应曲

21、线的时间常数。如果需要精确的锁相环和调制通道，就可以选择参数（1）。B 大信号模型最大偏差被一些因素所限制，这些因素与调制信号包络的非线性失真密切相关。这些失真出现在这些情况下：-电压或电流运算放大器的饱和度；-振荡器频率得到电压调整曲线角；-出现电压或电流运算放大器的动态失真。在第一种情况下，电压饱和度的最大偏差为：是运算放大器的饱和电压，为振荡器调整灵敏度，是闭合锁相环的传递函数。在第二种情况下，最大偏差等于平均振荡器频率和振荡器电压调制曲线最近角之间的距离的常数。第三种情况的最大偏差表达方式为其中S是运算放大器的转换速率。.校正的设计与测验图2显示了有无校正的调制通道的计算和实验频率响应

22、。锁相环的截止频率为100kHz，相位差度为-45度，振荡器调整灵敏度为-95MHz/V，振荡器滞后是不允许的。图2 调制通道的频率响应归到振荡器调整敏感度图3显示计算与实验频率响应的最大偏差的所有失真类型：实线为第一，点线为第二，链线为第三名。计算是由运算放大器AD829与Usat=12V组成的。平均振荡器频率和振荡器电压调制曲线最近角之间的距离是50MHz。从图2和图3看出，在最大偏差100KHz带有校正器的调频宽带是1，相对100KHz，5KHz是没有校正器的。与其他两个类型相比较，运算放大器中的动态失真是不出现的。在图2中，实验曲线接近计算值。在图3中，实验曲线与计算值不同是因为运算放

23、大器的电流饱和了。.结论在锁相环合成器中引用一个校正器，调制宽带可以相当大地被扩展。在这里，简单的图表解决方案和低成本的元素都可以使用。一个计算方法很简单，不像3中所描述的一个整合了最大频率偏差的计算。图3 最大偏差频率响应安德鲁.格里维俄罗斯SIBCON-2009西伯利亚控制与通信会议The Design of A Low-Power Low-Noise Phase Lock LoopAbstract :A phase lock loop is a closed-loop system that causes one system to track with another. More pr

24、ecisely, a PLL can be perceived as a circuit synchronizing an output signal with a reference or input signal in frequency as well as phase. High-performance phase lock loops are widely used within a digital system for clock generation, timing recovery, and to efficiently sequence operations and sync

25、hronize between function units and ICs As the digital system grows the role of phase lock loop increases. Achieving low jitter and phase noise in phase lock loop with less area and power consumption is challenging. The present research relates to characterization and redesign of individual blocks of

26、 Phase lock loop （PLL） to improve its characteristics. More specifically redesigning of individual blocks like: Phase Frequency Detector to reduce area and static phase error, Voltage to Current converter to linearly increase the current input to the current controlled oscillator, Current Controlled

27、 Oscillator to reduce phase noise, amplitude distortion, area and power consumption. We also introduce an additional feedback loop to increase the gain of the charge pump in a manner that linearizes the overall loop gain over wide bandwidth. The Results are substantial improvements in the PLL charac

28、teristics such as low jitter, phase noise, area and power consumption. Keywords:Phase Lock loop （PLL）, Phase Frequency Detector （PFD）, Voltage to Current converter （V2I）, Current Controlled Oscillator （ICO） 1. Introduction A PLL is essentially a negative feedback loop that locks the on-chip clock ph

29、ase to that of an input clock or signal 1. High-performance PLLs are widely used within a digital system for clock generation, timing recovery, and to efficiently sequence operations and synchronize between function units and ICs 2. Clock frequencies and data rates have been increasing with each gen

30、eration of processing technology and processor architecture. Within these digital systems, well-timed clocks are generated with phase-locked loops （PLLs） and then distributed on-chip with clock buffers. The rapid increase of the systems clock frequency poses challenges in generating and distributing

31、 the clock with low phase noise and low power 3. 2. PLL Definition A PLL can be perceived as a circuit synchronizing an output signal （generated by an oscillator） with a reference or input signal in frequency as well as phase 4. In the synchronized state, often referred to as “the locked state”, the phase error between the output signal and the input or reference signal remains constant or is zero However, if in the process due to some discrepancy a phas