数字信号处理控制器毕业论文外文翻译Word格式文档下载.docx

1、A serial communications interface （SCI） is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional communication interfaces; the 2407, 2406, and 2404 offer a 16-bit synchronous serial peripheral interface （SPI）. The 2407 and 24

2、06 offer a controller area network （CAN） communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also configurable as general purpose inputs/outputs （GPIO）.To streamline development time, JTAG-compliant scan-based emulation has been integrated into a

3、ll devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code generation tools from C compilers to the industry-standard Code Composerdebugger supports this family. Numerous third party developers not only offer device-level develo

4、pment tools, but also system-level design and development support.PERIPHERALSThe integrated peripherals of the TMS320x240x are described in the following subsections: Two event-manager modules （EVA, EVB）Enhanced analog-to-digital converter （ADC） moduleController area network （CAN） moduleSerial commu

5、nications interface （SCI） moduleSerial peripheral interface （SPI） modulePLL-based clock moduleDigital I/O and shared pin functionsExternal memory interfaces （LF2407 only）Watchdog （WD） timer moduleEvent manager modules （EVA, EVB）The event-manager modules include general-purpose （GP） timers, full-comp

6、are/PWM units, capture units, and quadrature-encoder pulse （QEP） circuits. EVAs and EVBs timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality avail

7、able for the event-manager modules and highlights EVA nomenclature. Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA

8、 nomenclature. These paragraphs are applicable to EVB with regard to functionhowever, module/signal names would differ. Table 1. Module and Signal Names for EVA and EVBEVENT MANAGER MODULESEVA MODULESIGNALEVB MODULEGP TimersTimer 1Timer 2T1PWM/T1CMPT2PWM/T2CMPTimer 3Timer 4T3PWM/T3CMPT4PWM/T4CMPComp

9、are UnitsCompare 1Compare 2Compare 3PWM1/2PWM3/4PWM5/6Compare 4Compare 5Compare 6PWM7/8PWM9/10PWM11/12Capture UnitsCapture 1Capture 2Capture 3CAP1CAP2CAP3Capture 4Capture 5Capture 6CAP4CAP5CAP6QEPQEP1QEP2QEP3QEP4External InputsDirectionExternal ClockTDIRATCLKINAExternal Clock TDIRBTCLKINBGeneral-pur

10、pose （GP） timersThere are two GP timers: The GP timer x （x = 1 or 2 for EVA; x = 3 or 4 for EVB） includes:A 16-bit timer, up-/down-counter, TxCNT, for reads or writesA 16-bit timer-compare register, TxCMPR （double-buffered with shadow register）, for reads or writesA 16-bit timer-period register, TxP

11、R （double-buffered with shadow register）, for reads or writesA 16-bit timer-control register,TxCON, for reads or writesSelectable internal or external input clocksA programmable prescaler for internal or external clock inputsControl and interrupt logic, for four maskable interrupts: underflow, overf

12、low, timer compare, and period interruptsA selectable direction input pin （TDIR） （to count up or down when directional up-/down-count mode is selected）The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compa

13、re function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager

14、submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer （PWM） period and the compare/PWM pulse width as needed. Full-com

15、pare unitsThere are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare r

16、egisters of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.Programmable deadband generatorThe deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values （from 0 to 24 s） can be program

17、med into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs （with or without deadband zone） for each compare unit output signal. The output sta

18、tes of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register.PWM waveform generationUp to eight PWM waveforms （outputs） can be generated simultaneously by each event manager: three independent pairs （six outputs） by the three full-compare units

19、with programmable deadbands, and two independent PWMs by the GP-timer compares.PWM characteristicsCharacteristics of the PWMs are as follows:16-bit registersProgrammable deadband for the PWM output pairs, from 0 to 24 sMinimum deadband width of 50 nsChange of the PWM carrier frequency for PWM freque

20、ncy wobbling as neededChange of the PWM pulse widths within and after each PWM period as neededExternal-maskable power and drive-protection interruptsPulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveformsMinimized CPU overhead using

21、 auto-reload of the compare and period registersCapture unit The capture unit provides a logging function for different events or transitions. The values of the GP timer 2 counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins,

22、CAPx （x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB）. The capture unit consists of three capture circuits.Capture units include the following features:One 16-bit capture control register, CAPCON （R/W）One 16-bit capture FIFO status register, CAPFIFO （eight MSBs are read-only, eight LSBs are writ

23、e-only）Selection of GP timer 2 as the time baseThree 16-bit 2-level-deep FIFO stacks, one for each capture unitThree Schmitt-triggered capture input pins （CAP1, CAP2, and CAP3）one input pin per capture unit. All inputs are synchronized with the device （CPU） clock. In order for a transition to be cap

24、tured, the input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1 and CAP2 can also be used as QEP inputs to the QEP circuit.User-specified transition （rising edge, falling edge, or both edges） detectionThree maskable interrupt flags, one for each capt

25、ure unitEnhanced analog-to-digital converter （ADC） moduleA simplified functional block diagram of the ADC module is shown in Figure 1. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold （S/H） circuit. Functions of the ADC module include:10-bit ADC core with built-in S/HFast conversio