1、A/D转换精度选择Bit 0 */byte SRES1A/D转换精度选择Bit 1 */byte ETRIGSELExternal Trigger Source Select */ Bits;/* ATD0CTL2 - ATD 0 Control Register 2; 0x000002C2 */byte ACMPIEATD Compare Interrupt Enable */byte ASCIEATD Sequence Complete Interrupt Enable */byte ETRIGEExternal Trigger Mode enable */byte ETRIGPExter
2、nal Trigger Polarity */byte ETRIGLEExternal Trigger Level/Edge control */byte ICLKSTPInternal Clock in Stop Mode Bit */byte AFFCATD Fast Conversion Complete Flag Clear*/byte /* ATD0CTL3 - ATD 0 Control Register 3; 0x000002C3 */byte FRZ0Background Debug Freeze Enable Bit 0 */byte FRZ1Background Debug
3、 Freeze Enable Bit 1 */byte FIFOResult Register FIFO Mode */byte S1CConversion Sequence Length 1 */byte S2CConversion Sequence Length 2 */byte S4CConversion Sequence Length 4 */byte S8CConversion Sequence Length 8 */byte DJMResult Register Data Justification */* ATD0CTL4 - ATD 0 Control Register 4;
4、0x000002C4 */byte PRS0ATD Clock Prescaler 0 */byte PRS1ATD Clock Prescaler 1 */byte PRS2ATD Clock Prescaler 2 */byte PRS3ATD Clock Prescaler 3 */byte PRS4ATD Clock Prescaler 4 */byte SMP0Sample Time Select 0 */byte SMP1Sample Time Select 1 */byte SMP2Sample Time Select 2 */ATD时钟的计算公式如下:ATDclock=BusC
5、lock/Prescaler/2/* ATD0CTL5 - ATD 0 Control Register 5; 0x000002C5 */byte CAAnalog Input Channel Select Code A */byte CBAnalog Input Channel Select Code B */byte CCAnalog Input Channel Select Code C */byte CDAnalog Input Channel Select Code D */byte MULTMulti-Channel Sample Mode */byte SCANContinuou
6、s Conversion Sequence Mode */byte SCSpecial Channel Conversion Bit */CD、CC、CB、CA:摸拟输入通道选择码:如果在单通采样模式(MULT=0),则这4位指定了目标通道;如果在多通道采样模式(MULT=1),则这4位指定了转换队列中的第一个通道,通过选择码的递加就可以得到队列中其他的通道,当选择码加到最大值时,则会回到最小值重新进行加操作。/* ATD0STAT0 - ATD 0 Status Register 0; 0x000002C6 */typedef union byte CC0Conversion Counter
7、 0 */byte CC1Conversion Counter 1 */byte CC2Conversion Counter 2 */byte CC3Conversion Counter 3 */byte FIFOROver Run Flag */byte ETORFExternal Trigger Overrun Flag */byte SCFSequence Complete Flag */CC4:0转换计数器:指向下一个将要转换的通道。/* ATD0STAT2 - ATD 0 Status Register 2; 0x000002CA */word Word;/* Overlapped
8、registers: */* ATD0STAT2H - ATD 0 Status Register 2 High;byte CCF8Conversion Complete Flag 8 */byte CCF9Conversion Complete Flag 9 */byte CCF10Conversion Complete Flag 10 */byte CCF11Conversion Complete Flag 11 */byte CCF12Conversion Complete Flag 12 */byte CCF13Conversion Complete Flag 13 */byte CC
9、F14Conversion Complete Flag 14 */byte CCF15Conversion Complete Flag 15 */* ATD0STAT2L - ATD 0 Status Register 2 Low; 0x000002CB */byte CCF0Conversion Complete Flag 0 */byte CCF1Conversion Complete Flag 1 */byte CCF2Conversion Complete Flag 2 */byte CCF3Conversion Complete Flag 3 */byte CCF4Conversio
10、n Complete Flag 4 */byte CCF5Conversion Complete Flag 5 */byte CCF6Conversion Complete Flag 6 */byte CCF7Conversion Complete Flag 7 */CCF15:0转换完成标志寄存器(写1清零)。/* ATD0DIEN - ATD 0 Input Enable Register; 0x000002CC */* ATD0DIENH - ATD 0 Input Enable Register High;byte IEN8ATD Digital Input Enable on cha
11、nnel 8 */byte IEN9ATD Digital Input Enable on channel 9 */byte IEN10ATD Digital Input Enable on channel 10 */byte IEN11ATD Digital Input Enable on channel 11 */byte IEN12ATD Digital Input Enable on channel 12 */byte IEN13ATD Digital Input Enable on channel 13 */byte IEN14ATD Digital Input Enable on
12、channel 14 */byte IEN15ATD Digital Input Enable on channel 15 */* ATD0DIENL - ATD 0 Input Enable Register Low; 0x000002CD */byte IEN0 ATD Digital Input Enable on channel 0 */byte IEN1ATD Digital Input Enable on channel 1 */byte IEN2ATD Digital Input Enable on channel 2 */byte IEN3ATD Digital Input Enable on channel 3 */byte IEN4ATD Digital Input Enable on channel 4 */byte IEN5ATD Digital Input Enable on channel 5 */byte IEN6ATD Digital Input Enable on channel 6 */byte IEN7ATD Digital Input Enable on channel 7 */IEN15:0ATD输出入允许寄存器。ATD0DR(word)15:0端口数据寄存器(当数据被取出的,转换完成标志位相应清零)。
copyright@ 2008-2022 冰豆网网站版权所有
经营许可证编号:鄂ICP备2022015515号-1