1、00110111 then-当分的低位为1或3或5或7时 q500=;-低频输出为1 else0-否则输出为0 end if; and s0= then-当秒高位为5，低位为9时且分高位为5，-分低位为9时，也就是“59分59秒”的时候“报时” qlk-高频输出为1end process;process（h1,h0,m1,m0,nao_h_h,nao_h_l,nao_m_h,nao_m_l） if dip（0）= and h1=nao_h_h and h0=nao_h_l and m1=nao_m_h and m0=nao_m_l then q1khzend behav;braz模块：use
2、ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity braz is port（ dip: f1khz,f500hz: braz:end entity;architecture behave of braz is begin process（q500,qlk,dip） if dip=0010 or dip=111010100110 then braz if q500=f500hz; elsif qlk= or q1khz=f1khz; else braz）;tens:full elsif （ones=） then ten
3、s:=tens+1;ones: one=ones; ten=tens; end process;end behave;显示模块：entity display is port （clk: a,b,c,d: mux_out: wei1,wei2,wei3,wei4:end display;architecture behave of display is signal sel:integer range 0 to 3; process（a,b,c,d,clk） if rising_edge（clk） then selmux_out=a; wei4wei3wei2wei1=b; when 2 =c;
4、 when 3=d; when others =1100 end case;消抖模块：entity debounce is port（key: key_valid:end debounce;architecture behave of debounce is process（clk,key） variable cnt:integer range 0 to 31; if （key= or key=10111101）then if（clk） then if cnt=31 then key_valid=23） then nao_h else nao_h=59） then nao_m else nao
5、_m nao_h_one when 2|12|22 = when 3|13|23= when 4|14=0100 when 5|15= when 6|16= when 7|17= when 8|18=1000 when 9|19=nao_h_one nao_h_ten when 20|21|22|23=nao_h_ten nao_m_one when 2|12|22|32|42|52 = when 3|13|23|33|43|53 = when 4|14|24|34|44|54 = when 5|15|25|35|45|55 = when 6|16|26|36|46|56 = when 7|1
6、7|27|37|47|57 = when 8|18|28|38|48|58 = when 9|19|29|39|49|59 =nao_m_one case nao_m is nao_m_ten when 30|31|32|33|34|35|36|37|38|39 = when 40|41|42|43|44|45|46|47|48|49 = when 50|51|52|53|54|55|56|57|58|59 =nao_m_teneight11111111分频模块：use ieee.std_logic_unsigned;entity fenpin is f1khz:end fenpin;arch
7、itecture behav of fenpin issignal mid:std_logic;variable cnum:integer range 0 to 25000; if （clk cnum:=cnum+1; if cnum=25000 then mid = not mid; cnum: f1khz=mid;1000分频模块：entity div1000 is port （clk: f1hz:architecture behav of div1000 is signal count:integer range 0 to 1000; count=count+1; if count=10
8、00 then f1hz else f1hz end if;分计数模块：entity mincount is ten : one :end mincount;architecture behave of mincount issignal min:signal min_temp:signal min_temp1:process（carry） if rising_edge（carry） then min_temp=min_temp+1; if（min_temp=59） then full min_temp min_temp1=59） then min_temp1 process（min）min=（min_temp+min_temp1） mod（60）; case min isone case min is ten小时计数模块：entit
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