1、 .OF(OF), .F(F), .M_R_Data(M_R_Data), .PC(PC) ); initial begin / Initialize Inputs rst = 0; clk_100MHz = 0; clk = 0; / Wait 100 ns for global reset to finish #100; / Add stimulus here forever begin #2; clk=clk; #10; clk_100MHz=clk_100MHz; end endendmodule顶层LED验证模块module TOP_LED(clk_100MHz,oclk,rst,S
2、W,LED);input clk_100MHz;input oclk,rst;input 3:0SW;output reg7:0LED;wire rclk;wire ZF,OF;wire 31:0F;0M_R_Data;0PC;xiaodou doudong(clk_100MHz,oclk,rclk);TOP_RIJ_CPU(rst,clk_100MHz,rclk,ZF,OF,F,M_R_Data,PC);always(*)begincase(SW)4b0000:LED=F7:0;b0001:LED=F15:8;b0010:LED=F23:16;b0011:LED=F31:24;b0100:L
3、ED=M_R_Data7:b0101:LED=M_R_Data15:b0110:LED=M_R_Data23:b0111:LED=M_R_Data31:b1000:begin LED7:2=0;LED1=OF;LED0=ZF;endb1100:LED=PC7:b1101:LED=PC15:b1110:LED=PC23:b1111:LED=PC31:default:LED=0;endcase顶层RIJ型指令CPU验证模块:module TOP_RIJ_CPU(input rst,input clk_100MHz,input clk,output ZF,output OF,output 31:0F
4、,output 31:0M_R_Data,output 31:0PC);wire Write_Reg;0Inst_code;wire 4:0rs;0rt;0rd;0rs_data;0rt_data;0rd_data;0imm_data;/被扩展的立即数wire 15:0imm;/wire rd_rt_s;wire 1:0w_r_s;wire imm_s;/判断是否需要扩展wire rt_imm_s;/B端选择rt或者是扩展后的immwire Mem_Write;/wire alu_mem_s;0wr_data_s;0W_Addr;0W_Data;0R_Data_A;0R_Data_B;0ALU
5、_B;/B端口数据wire 2:0ALU_OP;0PC_s;0PC_new;wire 25:0address;pc pc_connect(clk,rst,PC_s,R_Data_A,imm_data,address,Inst_code,PC);OP_YIMA op(Inst_code,ALU_OP,rs,rt,rd,Write_Reg,imm,imm_s,rt_imm_s,Mem_Write,address,w_r_s,wr_data_s,PC_s,ZF);assign W_Addr=(w_r_s1)?5b11111:(w_r_s0)?rt:rd);assign imm_data=(imm_s
6、)?16imm15,imm:161b0,imm;Register_file R_connect(rs,rt,W_Addr,Write_Reg,W_Data,clk,rst,R_Data_A,R_Data_B);assign ALU_B=(rt_imm_s)?imm_data:R_Data_B;ALU ALU_connect(R_Data_A,ALU_B,F,ALU_OP,ZF,OF);RAM_B Data_Mem ( .clka(clk_100MHz), / input clka .wea(Mem_Write), / input 0 : 0 wea .addra(F5:0), / input
7、5 : 0 addra .dina(R_Data_B), / input 31 : 0 dina .douta(M_R_Data) / output 31 : 0 douta); assign W_Data=(wr_data_s1)?PC_new:(wr_data_s0)?M_R_Data:F);PC取指令模块:module pc(input clk,input rst,input 1:0PC_s,input 31:0R_Data_A,input 31:0imm_data,input 25:0address,output 31:0Inst_code,output 31:reg 31:wire3
8、1:initial PC=32h00000000;Inst_ROM Inst_ROM1 ( .clka(clk), .addra(PC7:2), .douta(Inst_code) assign PC_new=PC+4;always(negedge clk or posedge rst) if(rst) else begin case(PC_s) 2b00:PC=PC_new;b01:=R_Data_A;b10:=PC_new+(imm_data2);b11:=PC_new31:28,address,2b00; endcaseOP指令功能译码模块:module OP_YIMA(inst,ALU
9、_OP,rs,rt,rd,Write_Reg,imm,imm_s,rt_imm_s,Mem_Write,address,w_r_s,wr_data_s,PC_s,ZF);0inst;output reg2:output reg4:output reg Write_Reg;output reg15:/output reg rd_rt_s;output reg imm_s;output reg rt_imm_s;output reg Mem_Write;output reg 25:output reg1:0 w_r_s;0 wr_data_s;0 PC_s;input ZF;/-处理R型指令-if
10、(inst31:26=6b000000) rd=inst15:11; rt=inst20: rs=inst25:21; /alu_mem_s=0; wr_data_s=2b00; Mem_Write=0; /rd_rt_s=0; w_r_s=2 rt_imm_s=0;case(inst5:0)6b100000:begin ALU_OP=3b100;Write_Reg=1;PC_s=2b100010:b101;b100100:b000;b100101:b001;b100110:b010;b100111:b011;b101011:b110;b000100:b111;b001000:Write_Re
11、g=0;b01;/-I型立即数寻址指令-29=3b001)imm=inst15:rt=inst20:rs=inst25:Mem_Write=0;/rd_rt_s=1;rt_imm_s=1;/alu_mem_s=0;w_r_s=2wr_data_s=2case(inst31:26)begin imm_s=1;ALU_OP=3b001100:begin imm_s=0;b001110:b001011:/-处理I型取数/存数指令-if(inst31:30=2b10)&(inst28:26=3b011)/rt寄存器/rs寄存器/rt作为目的存储器/imm作为源操作数imm_s=1;b100011:be
12、gin Mem_Write=0; Write_Reg=1;begin Mem_Write=1; Write_Reg=0;/-处理I型跳转指令-27=5b00010) imm=inst15:/rt/rs case(inst31: 6begin rt_imm_s=0; PC_s=(ZF?2b00);b000101:b10); /-处理J型跳转指令- if(inst31:b00001) address=inst25:b000010:begin w_r_s=2b11;b000011:b10;寄存器堆模块:module Register_file(R_Addr_A,R_Addr_B,W_Addr,Wri
13、te_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);input 4:0R_Addr_A;0R_Addr_B;input Write_Reg;input Clk;input Reset;output 31:0REG_Files0:31;reg 5:0i;initial/仿真过程中的初始化 for(i=0;i=31;i=i+1) REG_Filesi=0;assign R_Data_A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always(posedge Clk or posedge Reset) i
14、f(Reset) REG_Filesi=0; if(Write_Reg&W_Addr!=0) REG_FilesW_Addr=W_Data; endmoduleALU运算模块:module ALU(A,B,F,ALU_OP,ZF,OF);0A,B;input 2:output reg ZF,OF;output reg31:reg C32; OF=1b0; C32=1 case(ALU_OP) 3b000:F=A&B;b001:F=A|B;b010:F=AB;b011:F=(AB);b100:begin C32,F=A+B;OF=A31B31F31C32;b101:begin C32,F=A-B
15、;b110: if(AB) F=1; else F=0;b111:F=BA; if(F=0) ZF=1; ZF=0;二、仿真波形三、电路图 顶层电路模块 顶层电路内部结构:四、引脚配置(约束文件)NET LED7 LOC = T11;LED6 LOC = R11;LED5 LOC = N11;LED4 LOC = M11;LED3 LOC = V15;LED2 LOC = U15;LED1 LOC = V16;LED0 LOC = U16;SW3 LOC = M8;SW1 LOC = T9;SW0 LOC = T10;clk_100MHz LOC = V10;oclk LOC = C9;rst
16、 LOC = C4;SW2 LOC = V9;五、思考与探索(1)R-I-J型指令CPU实验结果记录表序号 指令 执行结果 标志 结论 1 00004020 $8=0000_0000 0 0 正确 2 00004820 $9=0000_0000 0 0 正确 3 200a0014 $10=0000_0014 0 0 正确 4 8d2b0010 $11=0000_0010 0 0 正确 5 010b4020 $8=0000_2222 0 0 正确 6 21290004 $9=0000_0004 0 0 正确 7 214affff $10=000_0013 0 0 正确 8 11400001 判断:$10不为0 0 0 正确 9 08000003 返回去执行地址为 0 0 正确 0000_0010的指令, 即序号4:8d2b0010 10 ac0b0030 存储器地址:0000_0030 0 0 正确
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