基于单片机的指纹识别电子密码锁设计英文资料和中文翻译文档格式.docx

1、FPGA is English Field Programmable Gate Array abbreviation, namely the scene programmable gate array, it is the product which in PAL, GAL, EPLD and so on in the programmable component foundation further develops. It is took in the special-purpose integrated circuit （ASIC） domain one kind partly has

2、custom-made, both solves has had custom-made the electric circuit which the electric circuit appears the insufficiency, and has overcome the original programmable component gate number limited shortcoming. FPGA used logical unit array LCA （Logic Cell Array） this kind of new concept, the interior inc

3、luding has been possible to dispose logical module CLB （Configurable Logic Block）, output load module IOB （Input Output Block） and internal segment （Interconnect） three parts. The FPGA essential feature mainly has:1） Uses FPGA to design the ASIC electric circuit, the user does not need to throw the

4、piece production, can obtain the chip which comes in handy. - - 2） FPGA may make other all to have custom-made or partly to have custom-made the ASIC electric circuit the experimental preview.2） The FPGA interior has the rich trigger and the I/O pin. 3） FPGA is in the ASIC electric circuit designs t

5、he cycle to be shortest, the development cost is lowest, one of risk smallest components.4） FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components.5） FPGA uses the high speed CHMOS craft, the power loss is low, may and C

6、MOS, the TTL level is compatible. It can be said that, the FPGA chip is the small batch system enhances the system integration rate, one of reliable best choices. FPGA is by deposits the procedure establishes its active status in internal RAM, therefore, time work needs to carry on the programming t

7、o internal RAM .The user may act according to the different disposition pattern, selects the different programming method. When adds the electricity, the FPGA chip the data read-in internal programs EPROM in RAM, after the disposition completes, FPGA thrust build-up .After falls the electricity, FPG

8、A restores the unsoldered glass, internal logic relations vanishing, therefore, FPGA can use repeatedly. The FPGA programming does not need the special-purpose FPGA programmer, only must use general EPROM, the PROM programmer then. When needs to revise the FPGA function, only must trade piece of EPR

9、OM then. Thus, identical piece FPGA, the different programming data, may have the different electric circuit function. Therefore the FPGA use is extremely flexible. FPGA has many kinds of disposition pattern: Parallel principal-mode -like is piece of FPGA adds piece of EPROM the way; The host may su

10、pport piece of PROM from the pattern to program multi-piece FPGA; The serial pattern may use serial PROM to program FPGA; The peripheral pattern may FPGA take the microprocessor the peripheral, programs by the microprocessor to it.In the electrical observation and control system, needs to gather eac

11、h kind of simulation quantity signal, the digital quantity signal frequently, and carries on corresponding processing to them. In the ordinary circumstances, in the observation and control system with ordinary MCU （for example 51, 196 and so on monolithic integrated circuits or control DSP） is may c

12、omplete the system task.。But when in the system must gather the signal quantity are specially many when （is specially each kind of signal quantity, condition quantity）, depends on merely with the ordinary MCU resources on often with difficulty completes the task。This time, generally only can adopt t

13、he multi-MCU in-line processing pattern, or depends on other chip expansion system resources to complete the system the monitor duty. Not only did this increased the massive exterior electric circuits and the system cost, moreover increased the system complexity greatly, thus the system reliability

14、could receive certain influence, this was not obviously the designer is willing to see. One kind based on the FPGA technology simulation quantity, digital quantity gathering and the processing system, uses FPGA the I/O port to be many, also may program the control freely, define its function the cha

15、racteristic, matches by VHDL the compilation FPGA interior execution software, can solve gathering signal way many problems well。Because compiles with VHDL the execution software interior to each group of digital quantity is according to the parallel processing, moreover the FPGA hardware speed is t

16、he ns level, this is a speed which current any MCU all with difficulty achieved, therefore this system compared to other systems can real-time, monitor the signal quantity fast the change。Therefore in the condition quantity specially many monitor system, this system will be able to display own super

17、iority.The practice proved that, Designs the DDS electric circuit with FPGA to use the special-purpose DDS chip to be more nimble. Because, so long as changes in FPGA the ROM data, DDS may have the random profile, thus has the quite big flexibility。Comparatively: The FPGA function is decided complet

18、ely by the design demand, may complex also be possible to be simple, moreover the FPGA chip also supports in the system scene promotes, although has the insufficiency slightly in the precision and the speed, but also can satisfy the overwhelming majority system basically the operation requirements.

19、Moreover, inserts the DDS design in the system which constitutes to the FPGA chip, its system cost cannot increase how many, but purchases the special-purpose chip the price is the former very many times. Therefore uses FPGA to design the DDS system to have the very high performance-to-price ratio.1

20、 Applications Emerge for Hybrid DevicesImplementation using an ASIC approach typically yields a faster, smaller, and lower power design than implementation in FPGA technology. The growing requirements in the marketplace for design flexibility however, are driving the need for hybrid ASIC/FPGA device

21、s. The potential to change hardware configuration in real time, to support multiple design options with a single mask set, and to prolong a products usable life, all compel designers to look for a blending of high density ASIC circuits along with the inherent FPGA circuit flexibility. The ability to

22、 create a “base design” and then reuse the base with minimal changes for subsequent devices helps reduce design time and encourages standardization. Since many consumer and office products are offered with a range of low to high-end options, this base design concept can be effectively used-with feat

23、ures added to each successive model. Printers, fax machines, PC s and digital imaging equipment are example where this concept can be useful DSP applications are also well suited to FPGA fast multiply and accumulate （MAC） processing capability. When building a DSP system, the design can take advanta

24、ge of parallel structures and arithmetic algorithms to minimize resources and exceed performance of single or multiple purpose DSP devices. DSP designers using both ASIC and FOGA within the same design can optimize a system for performance beyond the capabilities of either separate circuit technolog

25、y. Other applications that lend themselves to the hybrid ASIC/FPGA approach are designs that support multiple standards such as USB, Fire Wire and Camera LINK, in a single device. Similarly, designs that are finalized, with the exception of any undefined features or emerging standard, are excellent

26、candidates for this technology. Without the benefit of programmable logic, the designer must decide between taping-out the chip knowing that the PCI logic has a high probability for change, or waiting until the design requirements are firm-potentially impacting the end products schedule. With both p

27、rogrammable logic and ASIC working together on a single device, some situation like these can be accommodated. Other similar issues like differing geographic or I/O standards could also be incorporated within the FPGA cores, without requiring mask and fabrication updates for each change.10.2 Economi

28、cs Play a Role in Using Hybrid Devices While technical applications are emerging for the hybrid architecture, it is unlikely that design teams would utilize this new capability unless it is also economically viable. We will now explore the economics behind this new architecture. To realize the perfo

29、rmance and density advantages of an ASIC ,design teams must accept higher NRE and longer TAT than a FPGA. Unlike off-the-shift FPGA, each ASIC design requires a custom set of masks for silicon fabrication. The custom mask set allows circuitility and interconnections to be tailored to the requirement

30、s of each unique application-yielding high performance and density .However, the cost of the mask sets is rapidly increasing（nearly doubling with each successive technology node）.as a result, mask costs are becoming as significant portion of the per-die cost in many cases. For example, consider the

31、case wherere mask set costs $1,000,000.For applications where only 1,000 chip are required, each chip will over $1000, since the mask cost （plus many other expenses） must be amortized over the volume of chip sold. As the volume for this same ASIC rise, effective cost of each die decrease. Conversely

32、, FPGA are standard products, where the mask charges for small number of design passes are amortized over a large number of customers and chips, so the mask cost per chip sold is minimal. As a result, for each technology node there is a volume threshold, below which it more cost-effective to buy an FPGA chip vs. a smaller ASIC chip. TAT is another primary economic driver, having a direct impact on time-to-market for many applications. The time required for ASIC layout and fabrication is typically in the range 2-5months-much longer than FPGA, which generally requi