1、 u2 : h_adder port map (a=e, b=cin, co=f, so=sum); u3 : or2a port map (a=d, b=f, c=cout); end architecture fd1;2以下是含有使能端且具有同步清零的加减计数器的VHDL设计,试补充完整。use counter isport(updown,enable,clear,clk:in std_logic; q:out integer range 0 to 255);end counter;architecture a of counter isprocess(clk)variable cnt:i
2、nteger range 0 to (7) ;variable direction: (8) ; if (updown=1) then direction:=1; else (9) end if; if(clkevent and clk= if clear=0 then cnt:=0; if enable= (10) q=cnt;end process;end a; (7) 255 (8) integer (9) direction:= -1; (10) cnt:=cnt+direction1以下是8位分频器程序设计LIBRARY IEEE; USE PULSE IS PORT ( CLK :
3、 IN STD_LOGIC; D : IN STD_LOGIC_VECTOR (7 DOWNTO 0); FOUT : OUT STD_LOGIC );END;ARCHITECTURE one OF PULSE IS SIGNAL FULL : STD_LOGIC;BEGIN P_REG: PROCESS(CLK) VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF CLKEVENT AND CLK = 1 THEN IF CNT8 = THEN CNT8 := D; FULL = ; ELSE CNT8 := CNT8 + 1; FU
4、LL END IF; END IF; END PROCESS P_REG; P_DIV: PROCESS(FULL) VARIABLE CNT2 : IF FULLEVENT AND FULL = CNT2 = NOT CNT2; IF CNT2 = THEN FOUT ELSE FOUT END PROCESS P_DIV;1根据如下原理图,将相应VHDL描述补充完整。Library ieee;Use proj is Port (ain , bin , clk : Cout : (1) std_logic);End proj;Architecture one of (2) is Signal
5、 t1, t2: (3) ;begin (4) Process (clk) begin If clkevent and clk = 1 then t1 = bin;End process;Process ( (5) ) begin If (6) then cout = t2;end if;End one;2用元件例化语句设计如图3-1所示电路。LIBRARY ieee; -底层2输入与非门USE nand2 ISPORT(A1,B1: IN std_logic; C1: OUT std_logic);END nand2;ARCHITECTURE a1 OF nand2 IS C1=A1 NAN
6、D B1;END a1;-顶层设计USE yf4 ISPORT( A,B,C,D: Z:END yf4;ARCHITECTURE a OF yf4 IS COMPONENT nand2 PORT (A1,B1: END COMPONENT; SIGNAL X,Y: std_logic ; U1: nand2 PORT MAP (A,B,X); U2: nand2 PORT MAP (C,D,Y); U3: nand2 PORT MAP (X,Y,Z);END a;1.根据如图3-1所示原理图将相应的VHDL程序补充完整。Use yuanlitu is Port ( A, B, clk : Qo
7、ut :End yuanltu;Architecture behave yuanlitu is Signal s1, s2, s3:Begin s3 = s1 nand s2; Process (clk) Begin If clkevent and clk = 1 then s1 = A; s2 = B; End if; End process; Process (clk, s3) If clk = 1 then Qout =data then20 exit;21 else22 m1:=i+m1;23 m2:=i+m2;24 end if;25 end loop;26 ma=m1;mbdata
8、 then23行,改为m2:=i*i+m2;18位二进制数判奇电路中有三处错误,指出错误位置并改正。01 LIBRARY IEEE;02 USE 03 ENTITY p_check IS 04 PORT (a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);05 y:06 END p_check;07 ARCHITECTURE abc OF p_check IS 08 BEGIN 09 PROCESS (a)10 VARIABLE tmp: INTEGER;11 VARIABLE n:INTEGER;12 BEGIN 13 tmp:=14 FOR n in 0 TO 7 LO
9、OP 15 tmp:=tmp XNOR a(n);16 END LOOP;17 y=tmp;18 END PROCESS;19 END abc;10行,改为VARIABLE tmp:STD_LOGIC;11行,去掉15行,改为tmp:=tmp XOR a(n);2. 以下是时钟设计中模24计数器的VHDL设计,试补充完整。02 use use entity cnt24 is05 port(clk,clr:06 ten,one:out std_logic_vector(3 downto 0);07 co:out std_logic);08 end;09 architecture one of c
10、nt24 is10 signal ten_temp,one_temp:std_logic;11 begin12 process(clk,clr)14 if clr= then 15 ten_temp=000016 one_temp17 elsif clk18 if ten_temp=2 and one_temp=3 then 19 ten_temp20 one_temp21 elsif one_temp=9 then22 one_temp23 ten_temp=ten_temp+1;24 else one_temp=one_temp+1;25 end if;26 end if;27 end p
11、rocess;28 ten=ten_temp;29 one=one_temp;30 co when ten_temp=2 and one_temp=4 else 31 end;10行,改为signal ten_temp,one_temp:std_logic_vector(3 downto 0);30行,改为co clk, q = addr);19 U2 : myrom port map (addr = address, q = to_da);20 End one;13行,改为Component myrom19行,改为U2 : myrom port map (address = addr, q
12、=-分频系数为5、占空比为1:1的奇数分频器use div5 is port ( clk : div5 :end entity;architecture rtl of div5 issignal cnt1:std_logic_vector(2 downto 0);signal cnt2:signal clk_temp1:signal clk_temp2:constant m1:integer:=4; -计数器控制端1,m1=N-1constant m2:=2; -计数器控制端2,m2=(N-1)/2 process (clk) -上升沿触发计数器进程 if clk if cnt1=m1 the
13、n cnt1000 else cnt1 = cnt1 + 1; end if; end if; end process; process (clk) -下降沿触发计数器进程 if cnt2=m1 then cnt2 cnt2 = cnt2 + 1; process (clk) -上升沿触发计数器的计数控制进程 if cnt1=0 then clk_temp1 elsif cnt1=m2 then process (clk) -下降沿触发计数器的计数控制进程 if cnt2=0 then clk_temp2 elsif cnt2=m2 then div5=clk_temp1 or clk_tem
14、p2; -将两个计数器控制的信号采用或逻辑end rtl;-占空比不是1:1的偶数分频器,分频系数为6、占空比为1:5的分频器use div6 is port(clk : div6 :architecture rtl of div6 issignal cnt:signal clk_temp:constant m:=5; -控制计数器的常量,m=N-1 process (clk) if (rising_edge(clk) then if cnt=m then clk_temp cnt cnt = cnt + 1; div6=clk_temp;-分频系数为7、占空比为1:6的奇数分频器use div7 is port( clk : div7 :architecture rtl of div7 is=6; div7-分频系数不是2的整数次幂的分频器use div12 is div12 :architecture rtl of div12 is -控制计数器的常量,m=(N/2)-1=not clk_temp; -计数器值与m相等时clk_temp翻转 div12
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