1、EDA程序设计试题及答案1 请画出下段程序的真值表,并说明该电路的功能。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY aaa IS PORT( oe,dir :IN STD_LOGIC ; a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; END aaa ;ARCHITECTURE ar OF aaa ISBEGIN PROCESS(oe , dir ) 输入 输出 BEGIN a1 a0 x3 x2 x1 x0 IF oe=0 THEN a=”zzzzzzzz”; b=”zzzzzzzz”; 0 0 0
2、0 0 1 ELSIF oe=1 THEN 0 1 0 0 1 0 IF dir=0 THEN b=a; 1 0 0 1 0 0 ELSIF dir=1 THEN a=b; 1 1 1 0 0 0 ENDIF; END IF ; END PROCESS ;END ar ;功能为:24译码器.4分2 请说明下段程序的功能,写出真值表,并画出输入输出波形。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY aaa IS PORT( r
3、eset,clk: IN STD_LOGIC; q: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);END aaa;ARCHITECTURE bd OF aaa IS BEGIN PROCESS(clk,reset) BEGIN IF (reset=0) THEN q=000; ELSIF (clkevent AND clk=1) THEN IF (q=5) THEN q=000; ELSE q=q+1; END IF; END IF; END PROCESS;END bd;功能为:带进位借位的4位加/减法器。.3分输入输出波形图如下:7分ma3.0b3.0c3.0d
4、1. 试用VHDL语言编程实现74LS273芯片的功能。LIBRARY ieee; USE ieee.std_logic_1164.ALL; 2 ENTITY ls273 IS 1 PORT( clr, clk : IN std_logic; d : IN std_logic_vector(7 DOWNTO 0 ); q : OUT std_logic_vector(7 DOWNTO 0 ); 4 ); END ls273; ARCHITECTURE lock8 OF ls273 IS 1 BEGIN PROCESS ( clk ) 1 BEGIN IF (CLR=0) THEN q=”000
5、00000” ; 2 ELSEIF (clkevent AND clk=1) THEN q=d; 3 ELSEIF ( clk=0 ) THEN q=q; 1 END IF; END PROCESS; END lock8;3. 请用VHDL语言编程实现一个状态向量发生器。LIBRARY ieee; USE ieee.std_logic_1164.ALL; 2 ENTITY stas IS 1 PORT( cp, rst : IN std_logic; p : BUFFER std_logic_vector(7 DOWNTO 0 ); 2 ); END stas; ARCHITECTURE ar
6、stas OF stas IS 1 BEGIN PROCESS (cp ) 1 BEGIN IF(rst=”0”) THEN p=”00000000”; 1 ELSEIF (cpevent AND cp=1 ) 1WITH p SELECT pb THEN ahb=1; alb=0; aeb=0; ELSIF ab THEN ahb=0; alb=1; aeb=0; ELSE ahb=0; alb=0; aebb100ab010a=b001 (2)该电路是一个8位两输入比较器,(2)a、b是两个8位输入端;(1)ahb、alb和aeb为比较结果输出端,某种比较结果为真时,相应的输出端为“1”,
7、其余端输出为“0”。(2)1. 试用VHDL语言编程实现一个2-4译码器,其真表如下:输入端输出端enselecty0XX“1111”100“1110”101“1101”110“1011”111“0111” 2-4译码器码参考程序如下:(答案不唯一,用case语句、withselect语句都可以。)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; (1)ENTITY ym24 IS PORT( en : IN STD_LOGIC; select : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); y : OUT STD_LOGIC_VECT
8、OR(3 DOWNTO 0) (3);END ym24;ARCHITECTURE bd OF ym24 IS BEGIN PROCESS(en) (1) IF (en=1) THEN y= ”1110” WHEN select=”00” ELSE ”1101” WHEN select =”01” ELSE ”1011” WHEN select =”10” ELSE ”0111” WHEN select =”11” ELSE (4) ”1111”; ELSE yQQQQQQQ=00000000; (4) END CASE; END PROCESS;END bd; 2、已知三选一电路如图,判断下列
9、程序是否有错误,如有则指出错误所在,并给出完整程序。(10分)library ieee;use ieee.std_logic_1164.all;ENTITY MAX isport(a1,a2,a3,s0,s1:in bit; outy:out bit);end max; (2)architecture one of max iscomponent mux21a port(a,b,s:in std_logic; y:out std_logic);end component; (2)signal temp std_logic; (2)begin u1:mux21a port map(a2,a3,s0,temp); (2) u2:mux21a port map(a1,temp,s1,outy); (2) end one;1. 已知电路原理图如下,请用VHDL语言编写其程序答:library ieee;use ieee.std_logic_1164.all;entity mux21 is port(a,
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