1、VGA彩色显示器,彩色是由R、G、B(红、绿、蓝)三基色组成,CRT用逐行扫描方式实现图像显示,由VGA控制模块产生的水平同步信号(HS)和垂直同步信号(VS)控制阴极射线枪产生的电子束,打在涂有荧光粉的荧光屏上,产生R、G、B三基色,合成一个彩色像素。扫描从屏幕的左上方开始,由左至右,由上到下,逐行进行扫描,每扫完一行,电子束回到屏幕下一行的起始位置,在回扫期间,CRT对电子束进行消隐,每行结束是用行同步信号HS进行行同步;扫描完所有行,再由场同步信号VS进行场同步,并使扫描回到屏幕的左上方,同时进行场消隐,预备下一场的扫描。显示需要R,G,B,Hsync(行同步),Vsync(帧同步)五个
2、信号输出到显示器,本设计按照VGA工业标准输出640*48060Hz.对应的时序如下:图1 VGA接口信号基本时序图图2 FPGA板上的VGA接口图3 VGA(640*48060Hz)时序图VGA显示的设计模块为:说明:设计中FPGA板的VGA接口将R,G,B分别设为定义为2位,3位,3位,例如显示红色RGB可以输出为11000000,绿色输出为00111000,蓝色输出为00000111.表1 25MHz 640*48060Hz模式下VGA的时序5、代码 顶层模块包括4个模块,分别为分频div_clk、按键扫描keyscan、时序产生模块video_signal_gen、算法显示模块disp
3、_alg,其中分频模块有4个,分别输出25MHz、10kHz、50Hz、3s的时钟,25MHz是给video_signal_gen模块产生行时序和场时序的,10kHz是按键扫描的,50Hz是计算小方块的移动速度的时钟,3s是小方块背景变化时间。而div_clk模块是用实验一的模块,所以就不写测试代码测试了。1、顶层 按键先缓存2个时钟,为了消除亚稳态。其他就只是连线。module vga256( clk_50m, rst_p, key, vsync, hsync, vga_de, vga_b, vga_g, vga_r); input wire clk_50m; input wire rst_
4、p; input wire 2:0 key; output wire vsync; output wire hsync; output wire vga_de; output wire 1:0 vga_b; output wire 2:0 vga_g;0 vga_r; wire rst_n; assign rst_n = rst_p;/ /clock wire clk_25m; /25MHz VGA div_clk #( .cnt(2) ) u1div_clk ( .clk(clk_50m), .rst_n(rst_n), .f_clk(clk_25m) ); wire clk_10k; /1
5、0kHz keyscan .cnt(5000) u2div_clk .f_clk(clk_10k) wire clk_50hz; /50hz speed of movement .cnt(1000000) u3div_clk .f_clk(clk_50hz) wire clk_3s; /3s color translational speed .cnt(150) u4div_clk ( .clk(clk_50hz), .rst_n(rst_n), .f_clk(clk_3s) ); /key two buffers reg 2:0 key_r1;0 key_r2;0 key_r3; wire
6、2:0 key_val; always(posedge clk_10k or negedge rst_n) if(!rst_n) begin key_r1 = 3b000; key_r2 key_r3 end else= key;= key_r1;= key_r2; assign key_val = key_r3;/ & key_r2 & key_r1; wire 1:0 key1; /wire 2:0 key2;0 key3; keyscan u1keyscan( .clk(clk_10k), .rst_n(rst_n), .key(key_val), .key1(key1), /.key2
7、(key2), .key3(key3) ); wire 9:0 vga_x;0 vga_y; wire 7:0 vga_rgb; video_signal_gen b2v_inst1( .video_clk(clk_25m), .video_rgb(vga_rgb), .video_x(vga_x), .video_y(vga_y), .video_hsync(hsync), .video_vsync(vsync), .video_de(vga_de), .video_b(vga_b), .video_g(vga_g), .video_r(vga_r)/ disp_alg u1disp_alg
8、( .clk1(clk_25m), .clk2(clk_50hz), .clk3(clk_3s), .rst_n(rst_n), .key1(key1), .key3(key3), .video_x(vga_x), .video_y(vga_y), .video_rgb(vga_rgb) );endmoduleRTL图:图5.1.1 顶层模块RTL图1 图5.1.2 顶层模块RTL图2-2、div_clk模块代码 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;USE ieee.std_logic_un
9、signed.all;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity div_cl
10、k is generic (cnt : integer range 1 to 2*30 := 2*30); -分频系数 port( clk : in std_logic; rst_n : f_clk : out std_logic );end div_clk;architecture Behavioral of div_clk issignal sf_clk : std_logic := 0;begin process(clk,rst_n) variable i : integer range 0 to cnt := 0; begin if(rst_n = ) then i := cnt; s
11、f_clk if(clk event and clk = 1 i := i - 1; if(i cnt) then i : elsif(i = 0) then sf_clk = cnt/2 ) then else end if; end if; end if; end process; process(clk,sf_clk) if(cnt = 0) then f_clk elsif(cnt = 1) then= clk;= sf_clk;end Behavioral;3、keyscan模块代码 每按下按键一次就会产生一个脉冲,从而可以给算法来判断执行那个操作。module keyscan( c
12、lk, rst_n, key, key1, key2, key3 ); input clk; input rst_n; input 2: output 1: /times output 2: /back color count /select size, 60/80 width reg 1:0 key1_r;0 key2_r;0 key3_r;0 key1_pre;0 key2_pre;0 key3_pre; reg key1_r1; reg key1_r2; wire key1_pulse; reg key2_r1; reg key2_r2; wire key2_pulse; reg key
13、3_r1; reg key3_r2; wire key3_pulse; always(posedge clk or negedge rst_n) key1_r1 = 1b0; key1_r2 key2_r1 key2_r2 key3_r1 key3_r2 = key0;= key1_r1;= key1;= key2_r1;= key2;= key3_r1; assign key1_pulse = key1_r1 & (!key1_r2); assign key2_pulse = key2_r1 &key2_r2); assign key3_pulse = key3_r1 &key3_r2);
14、key1_r = 2b00; key2_r key3_r = key1_pre;= key2_pre;= key3_pre; assign key1_pre = key1_pulse ? (key1_r = 2b11) ? 2b00 : (key1_r + 2b01) : key1_r; assign key2_pre = key1_r1 ? (key2_pulse ? (key2_r = 3b111) ? 3 (key2_r + 3b001) : key2_r) : assign key3_pre = key1_r1 ? (key3_pulse ? (key3_r = 2 (key3_r +
15、 2 key3_r) : 1 assign key1 = key1_r; assign key2 = key2_r; assign key3 = key3_r;4、video_signal_gen时序产生模块在此模块中有输入有RGB,输出有横坐标X、纵坐标Y、行同步HS、场同步VS、使能DE、红色R值、绿色G值、蓝色B值。输入的RGB是为了给内部其他模块用的,可以根据输出的横坐标和纵坐标而改变屏幕的点的颜色。/ Description : 连接开发板的VGA接口和电脑液晶屏,/ 即可显示640*480分辨率下的256种色彩module video_signal_gen parameter HS
16、TS = 800, /all hsync times HSTDISP = 640, /hsync display times HSTPW = 96, /hsync pluse width times HSTFP = 16, /hsync front pluse times HSTBP = 48, /hsync back pluse times VSTS = 521, /all vsync pluse times VSTDISP = 480, /vsync display pluse times VSTPW = 2, /vsync pluse times VSTFP = 10, /vsync f
17、ront pluse times VSTBP = 29, /vsync back pluse times width_x = 10, /display x coordinate width width_y = 10 /display y coordinate width ( video_clk, rst_n, /ram interface video_rgb, video_x, /point coordinate video_y, /VGA transfer video_hsync, video_vsync, video_de, video_r, video_g, video_binput v
18、ideo_clk; / 25MHzinput rst_n; /reset/ram interfaceinput 7:0 video_rgb;output width_x-1 : 0 video_x;output width_y-1 : 0 video_y;/ FPGA与VGA接口信号output video_hsync; /行同步信号output video_vsync; /场同步信号output video_de; /vaildoutput2:0 video_r;0 video_g;output1:0 video_b;/-/ coordinate countreg width_x-1 : 0
19、 x_cnt; /行坐标wire width_x-1 : 0 x_cnt_pre;reg width_y-1 : 0 y_cnt; /列坐标wire width_y-1 : 0 y_cnt_pre;/generate x_cntalways(posedge video_clk or negedge rst_n) if(! x_cnt = width_x1b0; else= x_cnt_pre;assign x_cnt_pre = (x_cnt = HSTS - 1b1) ? width_x1b0 : (x_cnt + 1b1);/generate y_cnt y_cnt = width_y1= y_cnt_pre;assign y_cnt_pre = (y_cnt = VSTS - 1 width_y1 (x_cnt = HSTS - 1 (y_cnt + 1b1) : y_cnt);/generate hsyncreg hsync_r;wire hsync_r_p
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