1、USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY debounce IS PORT(key,cp: IN STD_LOGIC; -复位键 imp:OUT STD_LOGIC); -去掉窄波后输出END debounce;ARCHITECTURE base OF debounce ISSIGNAL ql,q2:STD_LOGIC;BEGIN PROCESS(cp) BEGIN IF cpevent AND cp=1THEN q2=ql; ql=key; END IF;END PROCESS; imp=ql AND NOT q2;END base;时序仿真波形:2、分频
2、电路USE IEEE.STD_LOGIC_SIGNED.ALL;ENTITY dividefre4 ISPORT(cp_2m:IN STD_LOGIC; -2MHz cpl:OUT STD_LOGIC; -200Hz cp2: -25Hz cp3: -5Hz END dividefre4;ARCHITECTURE behavior OF dividefre4 IS SIGNAL tout:INTEGER RANGE 0 TO 4999; -5000分频SIGNAL toutl:INTEGER RANGE 0 TO 7; -8分频SIGNAL tout2:INTEGER RANGE 0 TO 3
3、9; -40分频SIGNAL cp_1:SIGNAL cp_2:SIGNAL cp_3:SIGNAL cp: PROCESS(cp_2m) 分出400Hz时钟 IF(cp_2mevent AND cp_2m=)THEN IF tout=4999 THEN tout=0; ELSE tout=tout+1;IF tout=2499 THEN cp=0; ELSE cp END PROCESS; PROCESS(cp) -200Hz时钟 IF(cp cp_1=NOT cp_1; PROCESS(cp_1) -25Hz时钟和5Hz IF(cp_1event AND cp_1= IF toutl=7
4、THEN toutlELSE toutl=toutl+1; IF toutl=3 THEN cp_2 ELSIF toutl=7 THEN cp_2 -8分频得25Hz IF tout2=39 THEN tout2 -40分频得5Hz ELSE tout2=tout2+1; IF tout2=39 THEN cp_3 ELSIF tout2=19 THEN cp_3 cpl=cp_1;cp2=cp_2;cp3=cp_3;END behavior;仿真波形:(因原程序所分频倍数太大,所以这里将5000倍分频降至50倍)3、计数器ENTITY fretest ISPORT(enable: -使能
5、-闸门 INput: -被测信号 reset: -复位信号 overflow: -大于1000kHz Play0,playl,play2,play3:OUT INTEGER RANGE 0 TO 9; decimal:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);-小数点 ,即档位END fretest;ARCHITECTURE behavior OF fretest ISSIGNAL r0_1,r1_1,r2_1,r3_1,r4_1,r5_1: INTEGER RANGE 0 TO 9; PROCESS(INput,enable,reset,cp3) IF enable=
6、THEN NULL; -不测量 ELSIF(inputevent AND input=)THEN -检测被测信号 IF reset=THEN -同步复位,高电平有效 overflowr0_1r1_1 r2_1r3_1r4_1r5_1 ELSIF cp3=THEN -闸门为0时清零 Overflow ELSE -闸门为高电平计数=r0_1+1; IF r0_1=9 THEN r1_1=r1_1+1; IF(r1_1=9)THEN r2_1=r2_1+1; IF(r2_1=9)THEN r3_1=r3_1+1;r2_1 IF(r3_1=9)THEN r4_1=r4_1+1; IF(r4_1=9)T
7、HEN r5_1=r5_1+1; IF(r5_1=9)THEN r5_1overflowEND IF; PROCESS(r5_1,r4_1) IF r5_1=0 AND r4_1=0 THEN -为小于9999Hz时 play0=r0_1;playl=r1_1; play2=r2_1;play3=r3_1;decimal=100 ELSIF r5_1=0 THEN -为几十kHz时 =r4_1;010 ELSE -为几百kHz时=r5_1;001 END behavior;仿真波形4、锁存器ENTITY frelatch IS PORT(reset: -复位 -时钟 Overflow: -大于
8、1000kHz表示 play0,playl,play2,play3:IN INTEGER RANGE 0 TO 9;IN STD_LOGIC_VECTOR(2 DOWNTO 0);-小数点 overlatch: p0latch,pllatch,p21atch,p31atch: delatch:END frelatch;ARCHITECTURE behavior OF frelatch ISPROCESS(cp3,reset) overlatch p0latchpllatch p21atchp31atchdelatch=decimal; ELSIF cp3event AND cp3=overfl
9、ow;=play0;=playl;=play2;=play3; delatch5、显示模块ENTITY display ISPORT( cpl: -高于1000kHz标志 p0,p1,p2,p3:-BCD码输入 show:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-7段码输出 sel:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-位扫描码END dISplay;ARCHITECTURE behavior OF display ISSIGNAL count: INTEGER RANGE 0 TO 3;SIGNAL sel_1:STD_LOGIC_VE
10、CTOR(3 DOWNTO 0); PROCESS(cpl) IF(cplevent AND cpl=) THEN IF count=3 THEN countELSE countsel_11101 -第1位 WHEN 2=1011 -第2位 WHEN 3=0111 -第3位 END CASE;PROCESS(overflow,sel_1) IF(overflow=)THEN show0110111 -高于1000kHz,显示H ELSIF(sel_1(0)=)THEN -第0位数码管译码 CASE p0 ISshow0110011 WHEN 5=1011011 WHEN 6=0011111 WHEN 7=1110000WHEN 8=1111111 WHEN 9=1110011 ELSIF(sel_1(1)=)THEN -第1位译码 CASE p1 IS WHEN 8=ELSIF(sel_1(2)= )THEN -第2位译码 CASE p2 IS ELSIF(sel_1(3)=)THEN -第3位译码 CASE p3 ISWHEN 1= sel=sel_1;
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