1、3.5输入低压(VIL)1.5输出高压(VOH)4.44输出低压(VOD0.5共模电压(VT)2.5最Wj速率传输延退时间(25-50ns)耦合方式1.2LVCOMS 电平LVCOM&平参数3.63.32.70.7VCC0.2VCCVCC-0.10.10.5VCC2.1TTL电平20.82.4传输延退时间(5-10ns),2.2LVTTL 电平30.43.1LVDS 电平参数符号最小典型最大LVDS输出高电压V(n1 475LVDS辎出低电压0.925LVDS输出差分电压I&I250400洲LVDS在不同状态时 输出尺分电压波动A|Vo:|25神LVDS输出电压偏移蛇1J251.275LVDS
2、 土不同状冬时 输出屯压偏移址波动MJmV-VDS输出差分阻抗SO120CLVDS输出电流两丘分端相接12nA是分单端到地短路40mALVDS精入单端电斥苞田pv*LVDS时筹分信号灵植度100LVDS输入共模电流S三1,2V时350|JALVDS回滞门限宽度70eVLVDS输入件分阳抗Rin85 115Q最高速率:3.125Gbps耦合方式:4.1PECL(VCC=5V)/LVPECL(VCC=3.3V)电平参教最大值舶位输出高压Ta = 0C 至+蹈。Vcc- 1-025Vrr-0.S8Ta - -40Vet - 1.085Vci-0.88输出低压rA= u c 5+S5ffcV(x- L
3、81Vcc- 162Ta =Vre-LS3Vcc-1 55输入高田Vcc- 1.16VC( -0 88输入低哝Ver 1.81VCC-L4KLVPEC山10+Gbps5.1CML电平典梨授大养分输入电压408001000pmV |输出用模电斥P Vcc-0.2就输入电IL.范雨VisVec-0.6Vcc+0.2差分输入电旅摆幅WlVp*p10+GbpsVCC相同时CML与CML之间采用直流耦合,VCC不同时CML与CML 之间采用交流耦合6.1VML电平1.650.851.25VML电平与LVDS电平兼容,TLK2711输出是 VML电平。7.1HSTL 电平Tble t 1,512K瓯动需拦
4、桓田,压-3*3V-L V +3V演信器住钥巳压-TV + 7V-7V + 12V2DDR1 ,DDR2,DDR3DDR1DDR2DDR3电压 VDD/VDDQ2.5V/2.5V1.8V/1.8V (+/-0.1)1.5V/1.5V (+/-0.075)I/。接口SSTL_25SSTL_18SSTL_15数据传输率(Mbps)2004004。0 8008001600容量标准64M-1G256M -4G512M -8GMemory Latency(ns)15 2010-2010 15备注 CL值1.5/2/2.5/3314/5/65/6/7/B预取设计(Bit)8逻辑Bank数量2/44/88/
5、16突发长度2/4/8封装TSOPFBGA引脚标准184Pin DIMM240Pin DIMMDDR4:速率 1.63.2Gbps; I/。接口 SSTL_12 VDD 1.2V;3PCIE2. 0、PCIE3.0pa-e同规格/通道用念同比(箪向)PG E 1.xPQ-t 2.xPCt-E 3.0X12S0MB/S5 OOM B/sIGB/sx2SOOMB/s2GB/&x41GBA2GB/S4GB/SmS8GB/sxl4GB/s16GB/s参考时钟直流规Tiihle! 2 1: RlibCLCK DC Specificfitiuns and AC Tiniug RequiriKiilLsSy
6、mbol lajranLc I ej100 WT?: TfimitDniTwin M*Rise Edge Rat挡Rising Edge Rateo.a4.0V/niaFall Frige RalrFa Hung Frige RalfiOS4 QV/nsZ3VihDifTeierii-al inpui Hij- VoH tye+15DVlLDifferenl al input 1 wVtJllaqe-150VciTOK/VrwIutE crossing poiriT voltage+?50+5501 4.5VCROM-DELTAVariation of V3Rc:?i over all ris
7、ing dock MlgM+ n)mV 1 VrbRing-back Village Margin-100*100212TstablfTim已 hfifcirE Vitn is allowed500ps2,12Trcpicc avqAvi jge C ock PtfficxJ Actjicy-300+2汹pprn2J0JSTpEFioe A&9Absahte Penod (including Jitter and Spread Spectrumg47 1)203ns28Cycle in Gycle jinsr150VlWAXAb&3lJte Max input1517VmnAJbGlutE M
8、in inpul vollag-031.aDirty CycluDuty 喝 160%Rise-FsillMatchingRt.iig edge fdte (REFCLK+ ! Falk ng edgo rata (REPCLK-J mate hung201,14ZmcClock souitde DC impedancen1J1辅助信号直流规Ta7)le 2 3: Auxi 1 iar Signal DC Spe?cifications - PERSTfl,中AKF扎 3nd SMBijsSrnbol Piructc-rCondi t-ioiiisWinUni-tNotes海Inpul Low
9、 Vohege-fl & 0 8Vrninpul HighVcnafle20Vccs_3 + 0.5VuInoul Low Vcktiye-0 5s 0 fi-sInpul High VolragB2 1VccSue3_3 * 0-5VOL1Output LowVoltage4 0 mA021.3VhmaxMax High w#+ 0 5农Output Law VoHage4 0A。日1.4linInput LeakageCurrent0 ta 3 3 V-10+ 10MA2,4hhjgOutput 1 aakfle0 TO 3 3 V+50)5OrInpul PinCoptKi【顷心7pFC
10、jiOirtpin (kO PinCapAciiancft30*44USB2.0, USB3.0USB引脚定义接口型号引脚功能电线颜色USB2.01VBUS红D-白D+绿GND里 八、MicroUSB2.0IDB型悬空,A接地:USB3.0StdA_SSRX-蓝6StdA_SSRX+黄GND_DrainStdA_SSTX-紫StdA_SSTX+橙5SATA2.0, SATA3.0SAT觑取大市免理论速率SATA 1.01.5 Gbps150 MB/sSATA 2.03.0 Gbps300 MB/sSATA 3.06.0 Gbps600 MB/s6GTX高速接口M酗? 14: GTX Trans
11、celuflr DC SpecificationsDC ParaEutuCwidliticwiisMmTypMajUnitsWppaDifferential pik-lQ-peHk inpul 顽wgQEmmfil AC oouplEV(NM臼国山旧 input UDltagDG coupled .W 1 - -4PnMGTAVTTmvVqminCommon moa9 input EtagsDC coupled MGTA5T.LN2/3 MGTATTW/pPOJTDlflerefiilaJ p&ak-lci-peak outpul gRA 美 miransmmaT oupufl swing 垢
12、 sei lo nwdmurn Sefflftg1KM)VCMOUTDCDC common moCg output wHag&Equation tas-sdMGTAVTT DVppQy-p/4Dliltergntial inpul 睥s血neoflTijWf;,彳 GTX Transceiver DC SpedfloaHcns (Carttd)SyinbMDC P*rwn*l*rCodiliontTy(M林Unit*%ur功的mt# output island1100aO5K1EWTVana1-liter ou【Fpair iTXP and TXNj nlra.许 i Mew10PSCFKTneocn-fnended exlnnai AC coupling capac tlix*31HODrF
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