veriloghdl电子琴课程设计文档格式.docx

1、音乐的节拍通过分频变为4Hz，作为1/4拍。通过主模块调用各模块实现电子琴的功能。【关键词】Verilog HDL 电子琴 模块 分频ABSTRACTThis article introduced the simple electric pianos design. It realizes through the software and hardware union. The hardware system includes a director, 9 keys, LEDs and a buzzer. The software design uses Verilog HDL. Emulati

2、on uses Quartus II. It can broadcast the system establishment the corresponding note, and can complete a military song the broadcast, but also has shows the sound the function. Designs the simple electric piano to have in the hardware. The program has seven modules, including main module, fractional

3、 frequency module and so on. Keyboard with keys to play the function and replace the keys to play function. Key has seven sound, automatic playback function with three in song, were the two tiger , the sky city and kangding love songs. Software has its merit. It is perfect in the software Verilog HD

4、L. The original frequency is divided into different frequencys. The piano makes sound by the buzzer with different frequencys.【keywords】Verilog HDL electric piano module fractional frequency第一章 系统设计第一节 课题目标及总体方案本次项目设计课程的目标是让我们在学习Verilog HDL的基础上更加深入的理解硬件设计语言的功能、作用及其特征，并且将我们的动手能力与创新能力结合起来。本次电子琴实验的目标是：

5、1、具有手动弹奏和自动播放功能；2、以按键（或开关）作为琴键，至少可以通过蜂鸣器输出7个音阶；3、自动播放曲目至少两首；本次实验的方框图为：（每个模块中都有分频）第二节设计框图说明一、主模块主模块中用mm=（key8,key9）值的不同选择调用不同模块，mm=01调用曲目1模块，即bell模块；mm=10调用曲目2模块，即bell2模块；mm=11调用曲目3模块，即bell3模块；而在key8与key9没有被按下的情况下，程序调用按键模块，即digital_piano模块module main（inclk,outclk,key1,key2,key3,key4,key5,key6,key7,ke

6、y8,key9,num）;input inclk;input key1,key2,key3,key4,key5,key6,key7,key8,key9;output outclk;output3:0num;reg outclk,clk_6M;reg 3:0c;wire out1,out2,out3,out4;wire8:0 key;reg 1:0mm;assign key = key1,key2,key3,key4,key5,key6,key7,key8,key9; nclk（inclk）,.key1（key1）,.key2（key2）,.key3（key3）,.key4（key4）, .ke

7、y5（key5）,.key6（key6）,.key7（key7）,.beep2（out2）,.num（num）; bell m2（.inclk（inclk）,.beep1（out1）;bell2 m3（.inclk（inclk）,.beep3（out3）;bell3 m4（.inclk（inclk）,.beep4（out4）;always （posedge clk_6M） /在时钟的上升沿检测是否有按键按下begin if（key = 9b0） mm = 2b01; else if（key=9b1）b10;b11; else mm b00;end always（posedge inclk） b

8、egin if（c4d4） c=c+4d1; else begin=4d0; clk_6M=clk_6M; endalways （posedge clk_6M） if（mm = 2b01） outclk = out1; else if（mm = 2b00）= out2;b10）= out3; else outclk = out4;endendmodule二、按键模块Key1到key7对应do到si七个音，用于模拟电子琴弹奏/digital_piano子模块module digital_piano（inclk,key1,key2,key3,key4,key5,key6,key7,beep2,nu

9、m）;input inclk,key1,key2,key3,key4,key5,key6,key7;output beep2;wire 6:0 key_code;reg clk_6M;reg beep_r;reg 15:0 count;0 count_end;parameter Do = 7b1111110, /状态机的7个编码，分别对应中音的7个音符 re = 7b1111101, mi = 7b1111011, fa = 7b1110111, so = 7b1101111, la = 7b1011111, si = 7b0111111; assign key_code = key7,key

10、6,key5,key4,key3,key2,key1;assign beep2 = beep_r; /输出音乐always（posedge clk_6M） /分频模块，得出乐谱 count = count + 16 /计数器加1 if（count = count_end） count =16 /计数器清零 beep_r = !beep_r; always（posedge clk_6M） /状态机，根据按键状态，选择不同的音符输出 case（key_code） Do: count_end = 16d11450; re:d10204; mi:d09090; fa:d08571; so:d07802

11、; la:d06802; si:d06060; default:count_end endcasealways （posedge clk_6M） numb0001;b0010;b0011;b0100;b0101;b0110;b0111;二、曲目1模块/bell子模块 两只老虎module bell （inclk,beep1）; /系统时钟output beep1; /蜂鸣器输出端0high,med,low;0origin; /寄存器reg 7:0state; 0count;assign beep1=beep_r; /输出音乐/时钟频率6MHzreg clk_6MHz;reg 2:0 cnt1;

12、always（posedge inclk） if（cnt13 cnt1=cnt1+3b1; begin=3b0; clk_6MHz=clk_6MHz; end/时钟频率4MHzreg clk_4Hz;reg 24:0 cnt2; if（cnt225d6250000） cnt2=cnt2+25 cnt2=25 clk_4Hz=clk_4Hz;always （posedge clk_6MHz）= count + 1 /计数器加1 if（count = origin）h0; /输出取反always（posedge clk_4Hz） case（high,med,low） 12b000000010000

13、:origin=11466;/mid1b000000100000:origin=10216;/mid2b000000110000:origin=9101;/mid3b000001000000:origin=8590;/mid4b000001010000:origin=7653;/mid5b000001100000:origin=6818;/mid6b000000000101:origin=14447;/low5 endcasealways （posedge clk_4Hz） /歌曲 if（state =63） state = 0;/计时，以实现循环演奏 else state = state +

14、 1; case（state） 0,1: high,med,low=12b000000010000; 2,3: high,med,low=12b000000100000; 4,5:b000000110000; 6,7: 8,9: 10,11: 12,13: 14,15: 16,17: 18,19:b000001000000; 20,21,22,23:b000001010000; 24,25: 26,27: 28,29,30,31: 32: high,med,low=12 33: high,med,low=12b000001100000; 34: 35: 36,37: 38,39: 40: 41

15、: 42: 43: 44,45: 46,47: 48,49: 50,51:b000000000101; 52,53,54,55: high,med,low=12 56,56: 57,58: 59,60,61,62,63: default : high,med,low=12bx;三、曲目2模块/bell2子模块康定情歌module bell2 （inclk,beep3）;output beep3;assign beep3=beep_r; case（high,med,low） b000000000001:origin=22900; /低1 b000000000010:origin=20408; /

16、低2b000000000011:origin=18181; /低3origin=15267; /低5b000000000110:origin=13605; /低6b000000000111:origin=11472; /中1 /中2 /中3 /中5 /中6b0000:origin=5733; /高1origin=5108; /高2origin=4551; /高3always （posedge clk_4Hz） if（state =103） state = 0; state = state + 1; /康定情歌 case（state） high,med,low=/中3/中5/中6 6: high,med,low= 7: high,med,low= 8,9,10: 11: 12,13,14,15:/中2 20,21: high,m