1、 END PROCESS;4.2.1 D触发器的VHDL描述 【例4-6】LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY DFF1 IS PORT (CLK : IN STD_LOGIC ; D : Q : OUT STD_LOGIC ); END ; ARCHITECTURE bhv OF DFF1 IS SIGNAL Q1 : STD_LOGIC ; -类似于在芯片内部定义一个数据的暂存节点 PROCESS (CLK,Q1) IF CLKEVENT AND CLK = 1 THEN Q1 = D ; END PROCESS ;Q = Q1
2、 ; -将内部的暂存数据向端口输出(双横线-是注释符号) END bhv;4.3.1 半加器描述 【例4-16】LIBRARY IEEE; -半加器描述(1):布尔方程描述方法USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_adder IS PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC);END ENTITY h_adder;ARCHITECTURE fh1 OF h_adder is BEGIN so = NOT(a XOR (NOT b) ; co = a AND b ;END ARCHITECTURE fh1
3、;【例4-17】 -半加器描述(2):真值表描述方法PORT (a, b :SIGNAL abc:STD_LOGIC_VECTOR(1 DOWNTO 0);-定义标准逻辑位矢量数据类型 abc so=; co NULL ; END CASE;END ARCHITECTURE fh1 ;【例4-18】 LIBRARY IEEE ; -或门逻辑描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a ISIN STD_LOGIC; c : END ENTITY or2a; ARCHITECTURE one OF or2a IS c ain,b=bin,co=d,so=
4、e);-例化语句 u2 :e, b=cin, co=f,so=sum); u3 : or2a PORT MAP(a=d, b=f, c=cout); END ARCHITECTURE fd1;4.4四进制计数器设计【例4-20】ENTITY CNT4 IS PORT ( CLK : IN BIT ; BUFFER INTEGER RANGE 15 DOWNTO 0) ;END ;ARCHITECTURE bhv OF CNT4 IS BEGIN PROCESS (CLK) THEN Q 0) ; -计数器异步复位 ELSIF CLKEVENT AND CLK=1 THEN -检测时钟上升沿IF
5、 EN = 1 THEN -检测是否允许计数(同步使能) IF CQI 9 THEN CQI := CQI + 1; -允许计数,检测是否小于9 ELSE CQI :0); -大于9,计数值清零 IF CQI = 9 THEN COUT = 1; -计数大于9,输出进位信号 ELSE COUT = 0; CQ = CQI; -将计数值向端口输出END behav;4.5.3 含并行置位的移位寄存器设计 【例4-23】ENTITY SHFRT IS - 8位右移寄存器 PORT ( CLK,LOAD : DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB :END
6、 SHFRT;ARCHITECTURE behav OF SHFRT ISPROCESS (CLK, LOAD)VARIABLE REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0);IF CLK IF LOAD = THEN REG8 := DIN; -由(LOAD=)装载新数据 ELSE REG8(6 DOWNTO 0) := REG8(7 DOWNTO 1);END IF;QB = REG8(0); - 输出最低位END PROCESS;6.1.4 进程中的信号与变量赋值 【例6-1】USE IEEE.STD_LOGIC_1164.all ;ENTITY DFF3 IS
7、 PORT (CLK,D1 : Q1 :ARCHITECTURE bhv OF DFF3 IS PROCESS (CLK) VARIABLE QQ : THEN QQ := D1 ; Q1 = QQ;【例6-2】 ARCHITECTURE bhv OF DFF3 IS SIGNAL QQ : THEN QQ 【例6-3】 USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF3 IS PORT ( CLK,D1 : OUT STD_LOGIC ) ; SIGNAL A,B : PROCESS (CLK) BEGIN A B = A ;Q1 q = i1; when 2
8、 = i2; when 3 = i3; when others = null;end case;end process;END body_mux4;【例6-8】Library IEEE;ENTITY SHIFT IS PORT (CLK,C0 : -时钟和进位输入 MD : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -移位模式控制字 -待加载移位的数据 OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -移位数据输出 CN : -进位输出END ENTITY;ARCHITECTURE BEHAV OF SHIFT IS SIGNAL REG : SIG
9、NAL CY : BEGIN PROCESS (CLK,MD,C0) CASE MD IS001 REG(0) = C0 ;REG(7 DOWNTO 1) = REG(6 DOWNTO 0); CY -自循环左移 011 REG(7) = REG(0);REG(6 DOWNTO 0) = REG(7 DOWNTO 1); -自循环右移 100 REG(7) -带进位循环右移 101 REG(7 DOWNTO 0) = D(7 DOWNTO 0); -加载待移数 REG = REG ;= CY ; -保持 QB(7 DOWNTO 0) = REG(7 DOWNTO 0); CN = CY; -移
10、位后输出END BEHAV;6.2.1 三态门设计 【例6-9】ENTITY tri_s IS port ( enable : datain : dataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END tri_s ;ARCHITECTURE bhv OF tri_s ISPROCESS(enable,datain) IF enable = THEN dataout = datain ; ELSE dataout =ZZZZZZZZ END IF ;6.2.2 双向端口设计 【例6-10】library ieee;use ieee.std_logic_1
11、164.all;entity tri_state isport (control : in std_logic; in1: in std_logic_vector(7 downto 0); inout std_logic_vector(7 downto 0); x : out std_logic_vector(7 downto 0);end tri_state;architecture body_tri of tri_state isprocess(control,q,in1)if (control=) then x = q ;= else q = in1; x ZZZZZZZZ“;end i
12、f;end body_tri;6.2.3 三态总线电路设计 【例6-12】 ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END tristate2 ;ARCHITECTURE multiple_drivers OF tristate2 ISPROCESS(enable,input3,
13、input2, input1, input0 ) IF enable = THEN output = input3 ; ELSE output Z);= input2 ;IF enable = = input1 ;= input0 ;END multiple_drivers;数据溢出及其处理解决方法用并置符扩展位,但不能解决减法溢出的问题use ieee.std_logic_unsigned.all;entity arith_unsigned isPort(a,b:in std_logic_vector(3 downto 0); s1,s2:out std_logic_vector(4 dow
14、nto 0);end arith_unsigned;architecture one of arith_unsigned iss1=(&a)+(b);s2a)-(end;减法溢出的解决方法用并置符在数据前补符号位:数据前用并置符补符号位后,既解决了加法溢出的问题,也解决了减法溢出的问题!entity arith_signed isend arith_signed;architecture one of arith_signed is=(a(3)&a)+(b(3)&a)-(b(3)&8.1.3 一般有限状态机的设计 【例8-1】ENTITY s_machine IS PORT ( clk,reset : state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT INTEGER RANGE 0 TO 15 );END s_machine;ARCHITECTURE behv OF
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