1、int main() int i,j; WDTCTL = WDTPW + WDTHOLD;/ Stop WDT Init_TS3A5017DR(); / Configure TS3A5017DR IN1 and IN2 Init_lcd(); / LCD初始化 Backlight_Enable(); / 打开背光 LcdGo(1); / 打开液晶模块 LCD_Clear(); / 清屏 while(1) for (i=0; i6; i+) / Display 0123456 for(j=0;jj+) LCDMEMj = char_geni; delay_ms(1000); #include m
2、ath.h#define PI 3.1415926int sin_table360;int *sin_data_pr;double i=0;int j;void main(void) WDTCTL = WDT_MDLY_0_064; / WDT 61us interval timer SFRIE1 = WDTIE; / Enable WDT interrupt for(j=0;360; i+=PI/180; sin_tablej=(int)(sin(i)+1)*2048); sin_data_pr=&sin_table0; DAC12_0CTL0 = DAC12IR + DAC12SREF_0
3、 + DAC12AMP_5 + DAC12ENC + DAC12CALON+DAC12OPS; P5DIR=BIT1;/打开扬声器的运放 P5OUT&=BIT1; for (;) _bis_SR_register(CPUOFF + GIE); / Enter LPM0 DAC12_0DAT=*sin_data_pr+; if (sin_data_pr = &sin_table360) sin_data_pr = & / Positive ramp DAC12_0DAT &= 0xFFF; / Modulo 4096#pragma vector=WDT_VECTOR_interrupt void
4、 watchdog_timer (void) _bic_SR_register_on_exit(CPUOFF); / Clear LPM0 bits from 0(SR)int main(void) LCDMEM0 = char_gen3; LCDMEM1 = char_gen0; LCDMEM2 = char_gen0;52; i+=PI/26; sin_tablej=(int)(sin(i)+1)*2048);sin_table52)#define circnt100 1388#define circnt200 694#define circnt300 462#define circnt4
5、00 348#define circnt500 278#define circnt600 232#define circnt700 198#define circnt800 174#define circnt900 154#define circnt1000 138int sin_table180;const int cnt_table = circnt100,circnt200,circnt300,circnt400,circnt500,circnt600,circnt700,circnt800,circnt900,circnt1000;int cnt_flg = 0;void SetVco
6、reUp (unsigned int); / close watchdog /-p2.6- P2REN |= BIT6; / Enable P2.6 internal resistance P2OUT |= BIT6; / Set P2.6 as pullUp resistance P2IES |= BIT6; / P2.6 Hi/Lo edge P2IFG &= BIT6; / P2.6 IFG cleared P2IE |= BIT6; / P P2.6 interrupt enabled /*P2REN |= BIT7; P2OUT |= BIT7; P2IES |= BIT7; P2I
7、FG &= BIT7; P2IE |= BIT7; / P P2.6 interrupt enabled*/ /-enable LCD- LCDMEM5 = char_gen0; LCDMEM4 = char_gen0; LCDMEM3 = char_gen1; /-config sine list-180; i+=PI/90; sin_tablej=(int)(sin(i)+1)*2000); /- enable SMCLK as 8MHz- P4DIR |= BIT1; / P4.1 output P1DIR |= BIT0; / ACLK set out to pins P1SEL |=
8、 BIT0; P3DIR |= BIT4; / SMCLK set out to pins P3SEL |= BIT4; / Increase Vcore setting to level3 to support fsystem=25MHz / NOTE: Change core voltage one level at a time. SetVcoreUp (0x01); SetVcoreUp (0x02); SetVcoreUp (0x03); UCSCTL3 = SELREF_2; / Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; / S
9、et ACLK = REFO _bis_SR_register(SCG0); / Disable the FLL control loop UCSCTL0 = 0x0000; / Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; / Select DCO range 50MHz operation UCSCTL2 = FLLD_1 + 762; / Set DCO Multiplier for 25MHz / (N + 1) * FLLRef = Fdco / (762 + 1) * 32768 = 25MHz / Set FLL Div
10、= fDCOCLK/2 _bic_SR_register(SCG0); / Enable the FLL control loop / Worstcase settling time for the DCO when the DCO range bits have been / changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx / UG for optimization. / 32 x 32 x 25 MHz / 32,768 Hz 780k MCLK cycles for DCO to sett
11、le _delay_cycles(782000); / Loop until XT1,XT2 & DCO stabilizes In this case only DCO has to stabilize do UCSCTL7 &= (XT2OFFG + XT1LFOFFG + DCOFFG); / Clear XT2,XT1,DCO fault flags SFRIFG1 &= OFIFG; / Clear fault flags while (SFRIFG1&OFIFG); / Test oscillator fault flag /-enable timerA CCR0 us SMCLK
12、- TA0CCTL0 = CCIE; / CCR0 interrupt enabled TA0CCR0 = cnt_table0; TA0CTL = TASSEL_2 + MC_1 + TACLR; /use SMCLk as setting 25MHz _bis_SR_register(CPUOFF + GIE); DAC12_0DAT=*sin_data_pr+; if (sin_data_pr sin_table180) sin_data_pr = & DAC12_0DAT &void SetVcoreUp (unsigned int level) PMMCTL0_H = PMMPW_H
13、; / Open PMM registers for write / Set SVS/SVM high side new level SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; / Set SVM low side to new level SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; while (PMMIFG & SVSMLDLYIFG) = 0); / Wait till SVM is settled PMMIFG &= (SVMLVLRIFG + SVML
14、IFG); / Clear already set flags PMMCTL0_L = PMMCOREV0 * level; / Set VCore to new level if (PMMIFG & SVMLIFG) while (PMMIFG & SVMLVLRIFG) = 0); / Wait till new level reached / Set SVS/SVM low side to new level SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; / Lock PMM registers for
15、write access PMMCTL0_H = 0x00;/-timerA interruption-#pragma vector=TIMER0_A0_VECTOR_interrupt void TIMER0_A0_ISR(void)/-bottom interruption-#pragma vector=PORT2_VECTOR_interrupt void Port_2(void) cnt_flg+; if (cnt_flg = 10) cnt_flg = 0; if (cnt_flg = 9) LCDMEM3 = char_gen0; LCDMEM2 = char_gen1; else
16、 LCDMEM3 = char_gencnt_flg + 1; TA0CCR0 = cnt_tablecnt_flg;实验现象分析:LCD显示屏上循环显示0到6,每次显示都为6个相同的数字,现象对应的代码为:实验板上扬声器放出周期为64us*360=0.023s的正弦波信号。用示波器测量P7.6信号,测出信号频率为300HZ左右,LCD面板上显示为300。按下按键,信号频率按要求改变,同时LCD也显示出信号频率对应值。思考题1、MSP430系列单片机液晶驱动模块有哪些驱动方法?答:4种驱动方法:静态2mux3mux4mux2、MSP430系列单片机液晶驱动模块包括哪些功能结构?功能结构:具有显
17、示缓存器所需的SEG、COM信号自动产生多种扫描频率每个闪烁段都有独立的闪烁存储器稳压电荷泵软件实现反向控制显示缓存器可作为一般存储器3、MSP430系列单片机液晶驱动模块显示缓存有什么特点?和普通的存储单元有什么不同?特点:液晶显示缓存器各个位与液晶的段一一对应。存储位置位则可以点亮对应的液晶段,存储位复位液晶段变暗。段、公共极输出控制能够自动从显示缓存器读取数据,送出相应信号到液晶玻璃片上。因为不同器件驱动液晶的段数不同,所以液晶显示缓存器的数量也不一样。数量越大,驱动能力越强,显示的内容就越多。不同:显示缓存器可作为一般存储器,但一般存储单元存储位置位不可以点亮液晶段。4、常见液晶显示的
18、类型有哪些?段式液晶字符式液晶图形式液晶5、MSP430系列单片机液晶驱动模块有哪些特点?4种驱动方法 静态 2mux 3mux 4mux6、简述DAC的主要性能参数。分辨率(n):DAC转换器使用的位数, D/A转换器模拟输出电压可能被分离的等级数。输入数字量位数越多,分辨率越高。所以,在实际应用中,常用数字量的位数表示D/A转换器的分辨率。转换速度:转换速率(SR)在大信号工作状态下模拟电压的变化率。建立时间(tset)当输入的数字量发生变化时,输出电压变化到相应稳定电压值所需时间。最短可达0.1S。单调性:转换器的模拟输出值与数字输入值同增同减.偏移误差:当输入的数字量为0时,DAC输出的模拟量的大小。温度系数:在输入不变的情况下,输出模拟电压随温度变化产生的变化量。一般用满刻度输出条件下温度每升高1,输出电压变化的百分数作为温度系数。7、简述MSP430单片机DAC12模块的特点。12 位单调输出8位或12位电压输出分辨率可编程的时间对能量的消耗内部或外部参考电压二进制或二进制补码形式具有自校验功能多路DAC同步更新可直接用存储器存储(DMA)实验中遇到的问题无
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