1、010 elsif I(1) = 001 elsif I(0) = else0 end if; end process;end v1;/iframe8位相等比较器 - 8-bit Identity Comparator- uses 1993 std VHDLlibrary IEEE;use IEEE.Std_logic_1164.all;entity HCT688 is port(Q, P : in std_logic_vector(7 downto 0); GBAR : in std_logic; PEQ : out std_logic);end HCT688;architecture VE
2、R1 of HCT688 is PEQ when (To_X01(P) = To_X01(Q) and (GBAR = ) else end VER1;三人表决器(三种不同的描述方式) - Three-input Majority Voter- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. - download from: &ENTITY maj IS PORT(a,b,c : IN BIT
3、; m : OUT BIT);END maj;-Dataflow style architectureARCHITECTURE concurrent OF maj ISBEGIN -selected signal assignment statement (concurrent) WITH a&b&c SELECT m WHEN |, WHEN OTHERS;END concurrent;-Structural style architectureARCHITECTURE structure OF maj IS -declare components used in architecture
4、COMPONENT and2 PORT(in1, in2 : out1 : END COMPONENT; COMPONENT or3 PORT(in1, in2, in3 : -declare local signals SIGNAL w1, w2, w3 : BIT; -component instantiation statements. -ports of component are mapped to signals -within architecture by position. gate1 : and2 PORT MAP (a, b, w1); gate2 : and2 PORT
5、 MAP (b, c, w2); gate3 : and2 PORT MAP (a, c, w3); gate4 : or3 PORT MAP (w1, w2, w3, m);END structure;-Behavioural style architecture using a look-up tableARCHITECTURE using_table OF maj IS PROCESS(a,b,c) CONSTANT lookuptable : BIT_VECTOR(0 TO 7) :00010111 VARIABLE index : NATURAL; BEGIN index := 0;
6、 -index must be cleared each time process executes IF a = THEN index := index + 1; END IF; IF b = = index + 2; IF c = = index + 4;= lookuptable(index); END PROCESS;END using_table;加法器描述 - A Variety of Adder Styles- Single-bit adderuse IEEE.std_logic_1164.all;entity adder is port (a : b : cin : sum :
7、 out std_logic; cout :end adder;- description of adder using concurrent signal assignmentsarchitecture rtl of adder is sum = (a xor b) xor cin; cout a, in2 = b, out1 = xor1_out); xor2: xor1_out, cin, sum); and1: andg port map( and1_out); or1: org port map( or1_out); and2: or1_out, and2_out); or2: co
8、ut);end structural;- N-bit adder- The width of the adder is determined by generic Nentity adderN is generic(N : integer := 16); in std_logic_vector(N downto 1); out std_logic_vector(N downto 1);end adderN;- structural implementation of the N-bit adderarchitecture structural of adderN is component ad
9、der end component; signal carry : std_logic_vector(0 to N); carry(0) a(I), b = b(I), cin = carry(I - 1), sum = sum(I), cout = carry(I); end generate;- behavioral implementation of the N-bit adderarchitecture behavioral of adderN is p1: process(a, b, cin) variable vsum : std_logic_vector(N downto 1);
10、 variable carry : carry : for i in 1 to N loop vsum(i) := (a(i) xor b(i) xor carry;= (a(i) and b(i) or (carry and (a(i) or b(i); end loop;= vsum;= carry; end process p1;end behavioral;8位总线收发器:74245 (注2) - Octal Bus Transceiver- This example shows the use of the high impedance literal Z provided by s
11、td_logic.- The aggregate (others = ) means all of the bits of B must be forced to . - Ports A and B must be resolved for this model to work correctly (hence std_logic rather than std_ulogic). entity HCT245 is port(A, B : inout std_logic_vector(7 downto 0); DIR, GBAR : in std_logic);end HCT245;archit
12、ecture VER1 of HCT245 is= B when (GBAR = ) and (DIR = ) else (others =); B = A when (GBAR = 地址译码(for m68008) - M68008 Address Decoder- Address decoder for the m68008- asbar must be to enable any output- csbar(0) : X00000 to X01FFF- csbar(1) :4000043FFF- csbar(2) :080000AFFF- csbar(3) :E0000E01FFlibr
13、ary ieee;use ieee.std_logic_1164.all;entity addrdec is port( asbar : address : in std_logic_vector(19 downto 0); csbar : out std_logic_vector(3 downto 0) );end entity addrdec;architecture v1 of addrdec is csbar(0) = X) and (address ) else csbar(1) csbar(2) csbar(3) end architecture v1;多路选择器(使用select
14、语句) - Multiplexer 16-to-4 using if-then-elsif-else Statemententity mux is port( a, b, c, d: in std_logic_vector(3 downto 0); s: in std_logic_vector(1 downto 0); x: out std_logic_vector(3 downto 0);end mux;architecture archmux of mux ismux4_1: process (a, b, c, d) if s = 00 x = a; elsif s = 01= b;10=
15、 c;= d; end process mux4_1;end archmux;LED七段译码 - DESCRIPTION : BIN to seven segments converter- segment encoding- a- +-+ - f | | b- +-+ - g- e | | c- +-+- d- Enable (EN) active : high- Outputs (data_out) active : low- Download from :entity bin27seg is port ( data_in : in std_logic_vector (3 downto 0); EN : data_out : out std_logic_vector (6 downto 0)end entity;architecture bin27seg_arch of bin27seg is process(data_in, EN) data_out if EN= case data_in is when 0000 = data_out NULL; end case; end if;end architecture;多路选择器(使用ifelse语句) architecture archmux of
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