1、1.设计一个异或门(采用行为描述方式)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xor2_v1 IS PORT(a,b: IN STD_LOGIC; y: OUT STD_LOGIC);END xor2_v1;ARCHITECTURE behave OF xor2_v1 ISBEGIN y = a XOR b;END behave;2.编写一个8线3线编码器的VHDL程序(采用行为描述方式)ENTITY coder83_v1 IS PORT(I0,I1,I2,I3,I4,I5,I6,I7: A0,A1,A2:END coder83_v1;A
2、RCHITECTURE behave OF coder83_v1 ISBEGIN A2 = I4 OR I5 OR I6 OR I7; A1 = I2 OR I3 OR I6 OR I7; A0 = I1 OR I3 OR I5 OR I7;3.以74148逻辑表达式为依据,编写一个8线3线优先编码器的VHDL程序(行为)ENTITY prioritycoder83_v1 IS PORT(I7,I6,I5,I4,I3,I2,I1,I0 : EI:IN STD_LOGIC; A2,A1,A0: OUT STD_LOGIC; GS,EO:OUT STD_LOGIC);END prioritycod
3、er83_v1;ARCHITECTURE behave OF prioritycoder83_v1 IS= EI OR (I7 AND I6 AND I5 AND I4);= EI OR (I7 AND I6 AND I3 AND I2) OR (I7 AND I6 AND NOT I5) OR (I7 AND I6 AND NOT I4) ;= EI OR (I7 AND NOT I6) OR (I7 AND I5 AND NOT I4) OR (I7 AND I5 AND I3 AND I1) OR (I7 AND I5 AND I3 AND NOT I2); GS = EI OR (I7
4、 AND I6 AND I5 AND I4 AND I3 AND I2 AND I1 AND I0); EO Y 01111111 END CASE; ELSE Y 11111111 END IF; END PROCESS;ENDdataflow;5.编写一个8选1数据选择器的VHDL程序(IF语句)ENTITY mux8_v2 IS PORT(A: IN STD_LOGIC_VECTOR (2 DOWNTO 0); D0,D1,D2,D3,D4,D5,D6,D7: G: YB:END mux8_v2;ARCHITECTURE dataflow OF mux8_v2 IS PROCESS (A
5、,D0,D1,D2,D3,D4,D5,D6,D7,G) IF (G =) THEN= YB B) THEN YA YC ELSIF(A B) THEN 7.编写一个用“+”实现加法运算的8位加法器的程序USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY adder8_v IS PORT(A :IN STD_LOGIC_VECTOR(7 DOWNTO 0); B : Cin: Co : S :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END adder8_v;ARCHITECTURE behave OF adder8_v IS SIGNAL Si
6、nt : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL AA,BB:AA & A(7 DOWNTO 0);BB B(7 DOWNTO 0); Sint = AA + BB + Cin; S(7 DOWNTO 0) = Sint(7 DOWNTO 0); Co = Sint(8);8.编写一个8求补器的程序。library ieee; use ieee.std_logic_1164.all; entity hosuu is port( a: in std_logic_vector(7 downto 0); b: out std_logic_vector(7 downt
7、o 0); end hosuu; architecture rtl of hosuu is begin b=not a + 1;end rtl;9.编写一个三态门程序 entity tri_gate is port( din,en: in std_logic; dout : out std_logic); end tri_gate ; architecture zas of tri_gate is tri_gate: process(din,en) Begin if(en=1) then dout=din; else=Z; end if; end process; end zas;10.D 触
8、发器(带有异步置位复位功能)ENTITY d_ffy IS PORT( clk,d,set,reset : q,qd :OUT STD_LOGIC );END d_ffy;ARCHITECTURE a OF d_ffy IS PROCESS(clk,set,reset) IF (set= AND reset= q qd ELSIF (set= ELSIF (clkEVENT AND clk=d;=NOT d;END PROCESS;END a;11. jk 触发器(带有异步置位复位功能)USE IEEE.STD_LOGIC_1164.ALL ;ENTITY jk_asr_ff ISPORT (
9、 j , k ,clk ,set , res : IN STD_LOGIC ; q , qb : OUT STD_LOGIC ) ;END jk_asr_ff ;ARCHITECTURE behave OF jk_asr_ff IS SIGNAL q_temp : STD_LOGIC ; signal jk_temp : STD_LOGIC_VECTOR( 1 DOWNTO 0 ) ; jk_temp = j&k; PROCESS( clk , set , res ) IF set= THEN q_temp = ELSIF res = THEN q_temp ELSE IF( clkEVENT
10、 AND clk= ) THEN CASE jk_temp IS 01 q_temp X END CASE ; END IF ; END PROCESS ; q qb 12. 带有使能端的RS触发器ENTITY RSlatch IS PORT( r , s , en :IN BIT ; BUFFER BIT ) ;END RSlatch ;ARCHITECTURE rs_archi OF RSlatch ISSIGNAL s1 , r1 : BIT ; s1 = s NAND en ; r1 = r NAND en ; qb); IF (en= q ELSE qclk,d=d,q=q(i);
11、END GENERATE; g2: IF(i/=0) GENERATEq(i-1),q=END GENERATE ;ARCHITECTURE aa OF shiftb ISPROCESS(clk)IF(clk q(0) FOR i IN 1 TO n LOOP q(i)=q(i-1); END LOOP ;END IF;END aa;15. 循环移位寄存器ENTITY shiftx ISPORT( clk,load : IN STD_LOGIC; d : IN STD_LOGIC_VECTOR(3 DOWNTO 0); OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END
12、shiftx;ARCHITECTURE aa OF shiftx ISSIGNAL tmp : STD_LOGIC_VECTOR(3 DOWNTO 0);q=tmp; IF(load= tmp ELSE tmp(0)=tmp(3); tmp(3 downto 1)=tmp(2 downto 0);16.60进制递增计数器use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY cntm60v IS PORT( en : IN std_logic; clear : load : dl,dh : IN std_logic_
13、vector(3 downto 0); clk : cout : out std_logic; ql : buffer std_logic_vector(3 downto 0); qh : buffer std_logic_vector(3 downto 0) );END cntm60v;ARCHITECTURE behave OF cntm60v IS signal ent2 : std_logic; PROCESS (clk) VARIABLE tmpl,tmph :std_logic_vector(3 downto 0); IF(clear= tmpl:0000 tmph:=“0000”
14、; - -异步清零 ELSIF(clkEVENT AND clk = ) THEN IF load= THEN=dl;=dh; - - 同步置数 elsif(en=) then if (tmpl=1001 - -个位计数器9+1=0 if(tmph=0101 - -十位计数器5+1=0 59+1=0 else =tmph+1;=tmpl+1; end IF; -end lf (load) -end if clear ql = tmpl; ent2 = tmpl(3) and tmpl(0) and en; qh=tmph; cout=tmph(2) and tmph(0) and ent2; - -计数器为59时进位信号 cout 输出1。END behave ;1
copyright@ 2008-2022 冰豆网网站版权所有
经营许可证编号:鄂ICP备2022015515号-1