北科自动化数电pp7PPT课件下载推荐.ppt

1、输出输出不仅不仅取决于当取决于当前的输入前的输入还还与原来与原来的输出有关。的输出有关。组合电路、组合电路、记记忆元件忆元件。Slide 3组合逻辑电路组合逻辑电路（以第（以第3章逻辑门章逻辑门作为基本的逻辑作为基本的逻辑单元电路，在第单元电路，在第5、6章进行具体介绍）章进行具体介绍）时序逻辑电路时序逻辑电路（以第（以第7章触发器作章触发器作为基本的逻辑单元为基本的逻辑单元电路，在第电路，在第8、9介介绍不同的时序逻辑绍不同的时序逻辑电路）电路）逻辑代数基础（第逻辑代数基础（第4章）章）半导体存储器（第半导体存储器（第10章）章）Slide 47-1 Latches（7-1 Latches（

2、锁存器锁存器）7-2 Edge-Triggered Flip-Flops7-2 Edge-Triggered Flip-Flops（边沿触发器）（边沿触发器）7-3 Flip-Flop Operating Characteristic7-3 Flip-Flop Operating Characteristic（触发器的操（触发器的操作特性）作特性）7-4 Flip-Flop Application7-4 Flip-Flop Application（触发器的应用）（触发器的应用）7-5 One-shots7-5 One-shots（单稳态触发器）（单稳态触发器）7-6 The 555 Timer

3、7-6 The 555 Timer（555555定时器）定时器）The main difference between latches and The main difference between latches and filpfilp-flops is in the-flops is in the method used for changing the state.method used for changing the state.Both latches and flip-flops are Both latches and flip-flops are bistablebista

4、ble devices.devices.Slide 57-1 Latches（a type of temporary storage device）S-R（Set-Reset）latch（基本（基本R-SR-S触发器）触发器）Gated S-R latch（可控（可控R-SR-S触发器）触发器）同步同步S SR R触发器、主从触发器、主从J-KJ-K触发器（补充简介）触发器（补充简介）Gated D latch（可控（可控D D触发器）触发器）Slide 6&b&aFeedbackFeedbackS-R（Set-Reset）latchS-R（Set-Reset）latchIt can resi

5、de in either of two states using a feedback arrangement.Set means that the output is HIGH and reset means the output is LOWSlide 7&aLogic diagram:The output of each gate is connected to an input of the opposite gate.This produces the regenerative feedback that is characteristic of all latched and fl

6、ip-flops.Slide 8WHEN RD=1,SD=1Original State:10111001The present output:Original State:01110110The present output:&a&bOperationRemain the same state and no changeSlide 9WHEN RD=1,SD=00 or 110101For either of the original states,the output is：bSet means that the latch output is HIGH.Slide 100 or 1011

7、10For either of the original states,the output is：bWHEN RD=0,SD=1Reset means that the latch output is LOW.Slide 1100112.当当RD、SD同时由同时由0变为变为1时，翻转快的门输出变为时，翻转快的门输出变为0，另一个，另一个不得翻转。不得翻转。因此，该状态为因此，该状态为不定状态不定状态。b1111?1.The two outputs are not complement of each other.禁禁WHEN RD=0,SD=0Slide 12Two versions of

8、S-R latchesBoth of them should obey the rule:RDSD=0Slide 13 S-R latchSlide 14S-R latch 由它的功能表可见：由它的功能表可见：高电平有效时，若高电平有效时，若R、S不相等，不相等，Q 服从于服从于 S!Slide 15Slide 16Figure 77Figure 77 The 74LS279 quad latch.The 74LS279 quad latch.Thomas L.FloydThomas L.FloydDigital Fundamentals,9eDigital Fundamentals,9eCo

9、pyright 2006 by Pearson Education,Inc.Copyright 2006 by Pearson Education,Inc.Upper Saddle River,New Jersey 07458Upper Saddle River,New Jersey 07458All rights reserved.All rights reserved.Slide 17GatedGated S-R latch S-R latchSlide 18QQRDSDabRDSDcdRSCP“synchronous”means：the output will not change un

10、til CP is HIGH.Reset directlySet directlyoutputinputSynchronous S-R Flip-Flop 同步同步RS触发器触发器Slide 19QQRDSDabRDSDcdRSCPHigh level usuallyHigh level usuallyClear inputPreset inputasynchronous Preset and Clear inputsSlide 20Function descriptionIn brief:Qn+1-present output stateQn-prior state逻辑符号逻辑符号RS1R1

11、SC1QRDSDSlide 21同步触发器存在的问题：同步触发器存在的问题：CP1的全部时间里，输的全部时间里，输入信号都会引起触发器输出状态的变化，降低了电入信号都会引起触发器输出状态的变化，降低了电路的抗干扰能力。路的抗干扰能力。Slide 22CP1：master flip-flop works and slave flip-flop is locked.CP0：master flip-flop is locked and slave flip-flop worksOperation trait:master and slave flip-flop works alternatively

12、 in a whole CP periodF主主F从从RSQQ1R21S2C1CPQQQQ1R11S1C1CPMaster-Slave R-S Flip-Flop 主从主从RS触发器触发器Slide 23R S 触发器的电路结构演变过程触发器的电路结构演变过程由两个与非门构成基由两个与非门构成基本本RS触发器触发器由四个与非门构成同由四个与非门构成同步步RS触发器触发器由九个与非门构成主由九个与非门构成主从从RS触发器触发器公共结构公共结构让其接受让其接受时钟控制时钟控制解决抗干解决抗干扰问题扰问题Slide 24为了免除为了免除CP=1期间输入信号不许改变的限期间输入信号不许改变的限制，可采

13、用制，可采用边沿触发边沿触发方式。其特点是：触发器方式。触发器只在时钟跳转时发生翻转，而在只在时钟跳转时发生翻转，而在CP=1或或CP=0期期间，输入端的任何变化都不影响输出。间，输入端的任何变化都不影响输出。如果翻转发生在上升沿就叫如果翻转发生在上升沿就叫“上升沿触发上升沿触发”或或“正边沿触发正边沿触发”。如果翻转发生在下降沿。如果翻转发生在下降沿就叫就叫“下降沿触发下降沿触发”或或“负边沿触发负边沿触发”。The output changes states only at a specified point on the triggering input CP.目前广泛采用的触发器是这种

14、形式的结构。目前广泛采用的触发器是这种形式的结构。Slide 25（主从主从）JK触发器触发器CP1R21S2C1F从从1R11S1C1F主主KJJK触发器的触发器的功能最完善，功能最完善，有两有两条反馈条反馈线，没有约线，没有约束条件。束条件。希望希望RS触发器触发器在在R1和和S1时，输出也是时，输出也是确定的。确定的。Slide 26功能表功能表JK触发器的功能小结：触发器的功能小结：1.当当J=0、K=0时，具有保持功能；时，具有保持功能；2.当当J=1、K=1时，具有翻转功能；时，具有翻转功能；3.当当J=0、K=1时，具有复位功能；时，具有复位功能；4.当当J=1、K=0时，具有置

15、位功能。时，具有置位功能。逻辑符号逻辑符号C1Q1K1JSlide 27LatchesLatches Gated D latch（one input）EN=0，no change：EN=1，it is dependent on the D.Slide 28功能表功能表逻逻辑辑符符号号RS1DC1QRDSDSlide 29The 74LS75 quad gated D latches.The 74LS75 quad gated D latches.Slide 30Thomas L.FloydThomas L.FloydDigital Fundamentals,9eDigital Fundamentals,9eFigure 76Figure 76 The latch used to eliminate switch contact bounce.The latch used to eliminate switch contact bounce.Copyright 2006 by Pearson Education,Inc.Copyright 2006 by Pearson Education,Inc.Up