当前流行的商用芯片Word文档格式.docx

1、Like the Intel Pentium chip, of which the AMD Athlon is a clone with respect to Intels x86 Instruction Set Architecture, it is frequently used in clusters. Therefore we discuss this processor here although it is not used presently in integrated parallel systems. The Athlon processor has many feature

2、s that are also present in modern RISC processors: it supports out-of-order execution, has multiple floating-point units, and can issue up to 9 instructions simultaneously. A block diagram of the processor is shown in Figure 7 Figure 7: Block diagram of AMD Athlon processor. It shows that the proces

3、sor has three pairs of Integer Execution Units and Address Generation Units that via an 18-entry Integer Scheduler takes care of the integer computations and address calculations. Both the Integer Scheduler and the Floating-Point Scheduler are fed by the 72-entry Instruction Control Unit that receiv

4、es the decoded instructions from the instruction decoders. An interesting feature of the Athlon is the pre-decoding of x86 instructions in fixed-length macro-operations that can be stored in a Pre-decode Cache. This enables a faster and more constant instruction flow to the instruction decoders. Lik

5、e in RISC processors, there is a Branch Prediction Table assisting in branch prediction. The floating-point units allow out-of-order execution of instructions via the FPU Stack Map & Rename unit. It receives the floating-point instructions from the Instruction Control Unit and reorders them if neces

6、sary before handing them over to the FPU Scheduler. The Floating-Point Register File is 88 elements deep which approaches the number of registers as is available on RISC processors. The floating-point part of the processor contains three units: a Floating Store unit that stores results to the Load/S

7、tore Queue Unit and Floating Add and Multiply units that can work in superscalar mode, resulting in two floating-point results per clock cycle. Because of the compatibility with Intels Pentium III processors, the floating-point units also are able to execute Intel MMX instructions and AMDs own 3DNow

8、! instructions. However, there is the general problem that such instructions are not accessible from higher level languages, like Fortran 90 or C（+）. Both instruction sets are meant for massive processing of visualisation data and only allow for 32-bit precision to be used. The system bus complement

9、ing the Athlon processor is also faster than what is standardly available for Intel PIII processors: 200 MHz instead of 133 MHz. AMD claims the bus speed can be scaled to over 400 MHz. With the current clock frequency of 1-1.33 GHz of the current processors the Athlon is an interesting alternative f

10、or many of the RISC processors that are available at this moment. 2 Intel Pentium 4Although Pentium processors are not applied in integrated parallel systems these days, they play a major role in the cluster community as most compute nodes in Beowulf clusters are of this type. Therefore we briefly d

11、iscuss also this type of processor.Unfortunately, Intel only provides scant information on this new processor, not even enough to put together a reliable block diagram of the processor. Still, there a number of distinctive features with respect to the earlier Pentium generations. There are two main

12、ways to increase the performance of a processor: by raising the clock frequency and by increasing the number of instructions per cycle （IPC）. These two approaches are generally in conflict: when one wants to increase the IPC the chip will become more complicated. This will have a negative impact on

13、the clock frequency because more work has to be done and organised within the same clock cycle. Very seldomly chip designers succeed in raising both clock frequency and IPC simultaneously. Also in the Pentium 4 this could not be done. Intel has chosen for a high clock speed （initially about 40% more

14、 than that of the Pentium III with the same fabrication technology） while the IPC decreased by 10-20%. This still gives a net performance gain even if other changes would have been made to the processor. To sustain the very high clock rate that the present processors have, currently 1.7 GHz, a very

15、deep instruction pipeline is required. The instruction pipeline has no less than 20 stages, double the number of stages in that of the Pentium III. Although this favours a high clock rate, the penalty for a pipeline miss （e.g., a branch mis-predict） is much heavier and therefore Intel has improved t

16、he branch prediction by a increasing the size of the Branch Target Buffer from 0.5 to 4 KB. In addition, the Pentium 4 has an execution trace cache which holds partly decoded instructions of former execution traces that can be drawn upon, thus foregoing the instruction decode phase that might produce holes in the instruction pipeline.The primary cache is quite small by todays standards: 8 KB. This is again to accommodate the high clock spee