1、 lcd_rw : out std_logic);end counter;architecture Behavioral of counter iscomponent counter60 is resetn : out std_logic_vector(7 downto 0);end component;component decoder is Port (din:in std_logic_vector(3 downto 0 ); dout:out std_logic_vector(8 downto 0) );component lcd_interface is port ( clk : do
2、ut_s10 : in std_logic_vector (8 downto 0); dout_s1 : lcd_data : out std_logic_vector (7 downto 0); out std_logic ); signal ddout_s10 : std_logic_vector (8 downto 0); signal ddout_s1 : signal ddout : std_logic_vector (7downto 0);begin u1: counter60 port map(clk,resetn,ddout); u2: decoder port map(ddo
3、ut(7 downto 4),ddout_s10); u3: decoder port map(ddout(3 downto 0),ddout_s1); u4: lcd_interface port map(clk,resetn, ddout_s10,ddout_s1,dout,lcd_en, lcd_rs , lcd_rw);end Behavioral;- Company:- Engineer:- Create Date: 13:36:10 03/30/06- Design Name:- Module Name: count60 - Behavioral- Project Name:- T
4、arget Device:- Tool versions:- Description:- Dependencies:- - Revision:- Revision 0.01 - File Created- Additional Comments:entity counter60 isend counter60;architecture Behavioral of counter60 issignal count : std_logic_vector(7 downto 0);signal count_div : std_logic_vector (25 downto 0); dout = cou
5、nt; process (clk) begin if (clkevent and clk = 1) then if (resetn = 0 count_div ); else if (count_div (25) = ) then count_div ) ; else= count_div + 1; end if; end process; process(clk ,resetn) if resetn= then count elsif rising_edge(clk) then if (count_div (25) = if count(3 downto 0)=1001 count(3 do
6、wnto 0)=0000; count(7 downto 4)=count(7 downto 4) +1; else=count(3 downto 0)+1; if count=01011001 count dout100100000 ;end case;end process;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity lcd_interface isend lcd_interface;architecture lcd_interface_arch of lcd_interface issignal lcd_we_n : std_logic;signal lcd_en_int :signal
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