基于FPGA的液晶数字钟程序.docx

1、timescale 1ns / 1ps/ Company:/ Engineer:/ Create Date: 21:00:25 06/13/2011/ Design Name:/ Module Name: lcd1602shizhong/ Project Name:/ Target Devices:/ Tool versions:/ Description:/ Dependencies:/ Revision:/ Revision 0.01 - File Created/ Additional Comments:/module lcd1602shizhong(input clk,/input C

2、LOCK_50, / 板载时钟 50MHzinput rst, / 板载按键 RST/ LCD1602 Interfaceoutput 7:0 LCD1602_DATA, / LCD1602 数据总线output LCD1602_E, / LCD1602 使能output LCD1602_RS, / LCD1602 指令数据选择output LCD1602_RW, / LCD1602 读写选择input sw1,sw2,sw3,sw4,output led);/ 0 (8*16-1) = 128/ 16bits - 0123456789ABCDEF -wire 127:0 row1_val =

3、 the FPGA clock ;/wire 127:0 row2_val = Amy-studio Pub ;wire 3:0second_L,second_H;wire 3:0miniute_L,miniute_H;wire 3:0hour_L,hour_H;wire 3:0 sw_code;/ 例化 LCD1602 驱动/lcd1602_drive u0( .clk (clk),.rst (rst),/ LCD1602 Input Value.row1_val (row1_val),/.row2_val (row2_val),.second_L (second_L),.second_H

4、(second_H),.miniute_L (miniute_L),.miniute_H (miniute_H),.hour_L (hour_L),.hour_H (hour_H),/ LCD1602 Interface.lcd_data (LCD1602_DATA),.lcd_e (LCD1602_E),.lcd_rs (LCD1602_RS),.lcd_rw (LCD1602_RW);/ 时钟例化/watch watch(.clk (clk),.rst (rst),.sw_code (sw_code),.second_L (second_L),.second_H (second_H),.m

5、iniute_L (miniute_L),.miniute_H (miniute_H),.hour_L (hour_L),.hour_H (hour_H),.led (led);/按键例化/key key(.clk (clk),.rst (rst),.sw1 (sw1),.sw2 (sw2),.sw3 (sw3),.sw4 (sw4),.sw_code (sw_code);endmodule/lcd1602 驱动模块/module lcd1602_drive(input clk, / 50MHz时钟input rst, / 复位信号/ LCD1602 Input Valueinput 127:

6、0 row1_val, / 第一行字符/input 127:0 row2_val, / 第二行字符input 3:0second_L,input 3:0second_H,input 3:0miniute_L,input 3:0miniute_H,input 3:0hour_L,input 3:0hour_H,/ LCD1602 Interfaceoutput reg 7:0 lcd_data, / 数据总线output lcd_e, / 使能信号output reg lcd_rs, / 指令、数据选择output lcd_rw / 读、写选择);/ +/ 分频模块 开始/ +reg 15:0

7、cnt; / 计数子reg 7:0 date9:0;initialbegindate0=0;date1=1;date2=2;date3=3;date4=4;date5=5;date6=6;date7=7;date8=8;date9=9;endalways (posedge clk, negedge rst)if (!rst)cnt = 0;elsecnt = cnt + 1b1;/ 500Khz 1MHz 皆可wire lcd_clk = cnt15; / (216 / 50M) = 1.31ms/ -/ 分频模块 结束/ -/ +/ LCD1602 驱动模块 开始/ +/ 格雷码编码共 40

8、 个状态parameter IDLE = 8h00;/ 写指令初始化parameter DISP_SET = 8h01; / 显示模式设置parameter DISP_OFF = 8h03; / 显示关闭parameter CLR_SCR = 8h02; / 显示清屏parameter CURSOR_SET1 = 8h06; / 显示光标移动设置parameter CURSOR_SET2 = 8h07; / 显示开及光标设置/ 显示第一行parameter ROW1_ADDR = 8h05; / 写第 1 行起始地址parameter ROW1_0 = 8h04;parameter ROW1_

9、1 = 8h0C;parameter ROW1_2 = 8h0D;parameter ROW1_3 = 8h0F;parameter ROW1_4 = 8h0E;parameter ROW1_5 = 8h0A;parameter ROW1_6 = 8h0B;parameter ROW1_7 = 8h09;parameter ROW1_8 = 8h08;parameter ROW1_9 = 8h18;parameter ROW1_A = 8h19;parameter ROW1_B = 8h1B;parameter ROW1_C = 8h1A;parameter ROW1_D = 8h1E;par

10、ameter ROW1_E = 8h1F;parameter ROW1_F = 8h1D;/ 显示第二行parameter ROW2_ADDR = 8h1C; / 写第 2 行起始地址parameter ROW2_0 = 8h14;parameter ROW2_1 = 8h15;parameter ROW2_2 = 8h17;parameter ROW2_3 = 8h16;parameter ROW2_4 = 8h12;parameter ROW2_5 = 8h13;parameter ROW2_6 = 8h11;parameter ROW2_7 = 8h10;parameter ROW2_8

11、 = 8h30;parameter ROW2_9 = 8h31;parameter ROW2_A = 8h33;parameter ROW2_B = 8h32;parameter ROW2_C = 8h36;parameter ROW2_D = 8h37;parameter ROW2_E = 8h35;parameter ROW2_F = 8h34;reg 5:0 current_state, next_state; / 现态、次态/ FSM: always1always (posedge lcd_clk, negedge rst)if(!rst) current_state = IDLE;e

12、lse current_state = next_state;/ FSM: always2alwaysbegincase(current_state)IDLE : next_state = DISP_SET;/ 写指令初始化DISP_SET : next_state = DISP_OFF;DISP_OFF : next_state = CLR_SCR;CLR_SCR : next_state = CURSOR_SET1;CURSOR_SET1 : next_state = CURSOR_SET2;CURSOR_SET2 : next_state = ROW1_ADDR;/ 显示第一行ROW1_ADDR : next_state = ROW1_0;ROW1_0 : next_state = ROW1_1;ROW1_1 : next_state = ROW1_2;ROW1_2 : next_state = ROW1_3;ROW1_3 : next_state = ROW1_4;ROW1_4 : next_state = ROW1_5;ROW1_5 : next_state = ROW1_6;ROW1_6 : next_state = ROW1_7; ROW1_7 : next_sta