实验1EDA工具的使用Word下载.docx

1、模型创建、添加用户约束文件、创建一个Vivado工程、输入所创建的电路模型、对用户约束文件添加约束、行为仿真、设计综合、设计实现、生成下载文件，最后是将下载文件下载到硬件平台上进行实际验证。图1 设计流程图二、实验内容1. 创建一个Vivad工程，对设计源文件进行分析；2. 使用XSim仿真器对设计进行仿真；3. 设计综合；4. 设计实现；5. 进行时序仿真；6. 生成下载文件。三、实验步骤使用现成的设计文件针对XC7A100TCSG324C-1器件完成整个设计流程。电路如图2所示，部分输入通过逻辑处理后送到输出。具体操作步骤如下：图2 整个电路图3.1 用IDE创建一个Vivado工程1.

2、Open Vivado by selecting Start All Programs Xilinx Design Tools Vivado 2014.2 Vivado 2014.22. Click Create New Project to start the wizard. You will see Create A New Vivado Project dialog box. Click Next.3. Click the Browse button of the Project location field of the New Project form, browse to, for

3、 example d:Lab1_source, and click Select.4. Enter tutorial in the Project name field. Make sure that the Create Project Subdirectory box is checked. Click Next. 5. Select RTL Project option in the Project Type form, and click Next. 6. Select Verilog as the Target language and Simulator language in t

4、he Add Sources form. 7. Click on the Add Filesbutton, browse to the d:Lab1_source directory, select tutorial.v, click Open, and then click Next. 8. Click Next to get to the Add Constraints form. 9. Click Next if the entry is already auto-populated, otherwise click on the Add Filesbutton, browse to t

5、he d:Lab1_source directory and select tutorial.xdc, and click Open. 10. In the Default Part form, using the Parts option and various drop-down fields of the Filter section, select the XC7A100TCSG324-1 part. Click Next.11. Click Finish to create the Vivado project.12. Open the tutorial.v source and a

6、nalyze the content.13. Open the tutorial.xdc source and analyze the content.14. Perform RTL analysis on the source file. Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator pane and click on Schematic. The model （design） will be elaborated and a logic view of t

7、he design is displayed. Notice that some of the switch inputs go through gates before being output to LEDs and the rest go straight through to LEDs as modeled in the file.3.2 用XSim Simulator对设计进行仿真1. Add the tutorial_tb.v testbench file. Click Add Sources under the Project Manager tasks of the Flow

8、Navigator pane. Select the Add or Create Simulation Sources option and click Next. In the Add Sources Files form, click the Add Files Button. Browse to the d:Lab1_source folder and select tutorial_tb.v and click OK. Click Finish. 2. Select the Sources tab and expand the Simulation Sources group. The

9、 tutorial_tb.v file is added under the Simulation Sources group, and tutorial.v is automatically placed in its hierarchy as a tut1 instance. 3. Double-click on the tutorial_tb in the Sources pane to view its contents. The testbench defines the simulation step size and the resolution in line 1. The t

10、estbench module definition begins on line 5. Line 15 instantiates the DUT （device/module under test）. Lines 17 through 26 define the same module functionality for the expected value computation. Lines 28 through 39 define the stimuli generation and compares the expected output with what the DUP prov

11、ides. Line 41 ends the testbench. The $display task will print the message in the simulator console window when the simulation is run.4. Simulate the design for 200 ns using the XSim simulator. Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane. A Project Settings

12、form will appear showing the Simulation properties form. Select the Simulation tab, and set the Simulation Run Time value to 200ns and click OK. Click on Run Simulation Run Behavioral Simulation under the Project Manager tasks of the Flow Navigator pane. The testbench and source files will be compil

13、ed and the XSim simulator will be run （assuming no errors）. You will see a simulator output similar to the one shown below. 5. Click on the Zoom Fit button （） located left of the waveform window to see the entire waveform.6. Change display format if desired. Select i31:0 in the waveform window, righ

14、t-click, select Radix, and then select Unsigned Decimal to view the for-loop index in integer form. Similarly, change the radix of switches7:0 to Hexadecimal. Leave the leds7:0 and e_led7:0 radix to binary as we want to see each output bit.7. Add more signals to monitor lower-level signals and conti

15、nue to run the simulation for 500 ns. Expand the tutorial_tb instance, if necessary, in the Scopes window and select the tut1 instance. The swt7:0 and led7:0 signals will be displayed in the Objects window. Select swt7:0 and drag them into the waveform window to monitor those lower-level signals. On the simulator tool buttons ribbon bar, type 500 in the time window, click on the drop-down button of the units field and select ns, and click on the （） button.8. The simulation will run for an additional 500 ns. Click on the Zoom Fit button and obser