嵌入式项目开发过程PPT格式课件下载.ppt

1、第二成员：记录与提问其他技术人员：参与探讨并形成产品蓝图列出必做适宜清单，找到设计产品的共同蓝图,嵌入式项目设计生命周期（二）硬件与软件的划分,观点：软硬件是可以互相替换的如：浮点运算与浮点处理器（FPU）等两种不同的划分策略优化处理器能力和软件通过ASIC设计找到解决途径划分中需要考虑的许多需求价格低、性能领先、市场竞争、知识产权等CPU的选择将影响划分决策和开发工具选择,嵌入式项目设计生命周期（三）迭代与实现,迭代与实现阶段的主要特点：主要障碍可能还是在软硬件的详细划分上设计约束被深刻理解和建模保留软硬件划分之间的余地软硬件设计人员之间的迭代结构体系模拟器：Simulator评估板或开发板

2、：Evaluation Board目的：减小设计阶段后期风险,嵌入式项目设计生命周期（四）详细的硬件与软件设计文档管理,这里不详细讨论软硬件设计问题大部分同学在其他课程中学到的C/C+/JAVA编程技术、数字设计和微处理器知识使他们有足够的机会解决设计中遇到的问题文档管理与质量控制设计复用和可视化减小设计修改成本有助于测试和质量控制,嵌入式项目设计生命周期（五）硬件与软件集成,Not a easy ProblemBig Endian/Little Endian引发的问题调试过程及实时系统调试方法带来的一些问题等嵌入式系统设计中软硬件集成的理想状态由第一个硬件原型、应用软件、驱动代码、操作系统设

3、计出完美的系统没有致命错误没有飞线不用重新设计ASIC或FPGA没有太多的软件设计修改,嵌入式项目设计生命周期（六）产品测试与发布,嵌入式产品测试具有特殊的意义人们或许可以容忍PC偶然死机，但是核电站报警系统？！导弹控制系统？PC外围硬件Is there any problem with you?测试的目的不仅是确信软件不会在关键时刻崩馈还必须查明是否在运行时能接近最优性能，尤其是用高级语言编写或多个开发人员编写的程序每个微小的错误都可能是致命的如轻微内存泄漏，长时间运行才能发现的问题等,嵌入式项目设计生命周期（七）产品维护和升级,产品维护的模式维护/支持小组!设计小组维护详细文档经验技巧上一

4、代产品产品升级的巨大代价理解原设计人员的思路与代码反向逆推并改进原始设计小组的工作需要非凡的技艺或强大的反向设计工具否则，不如开始新的设计，这是原供应商和生产上所不愿意看到的,主要内容,嵌入式设计生命周期选择过程划分决策详细的硬件与软件设计嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程开发、调试环境与工具,选择过程处理器平台,选择处理器是一个复杂的工作，它不仅是一个简单的“优化”问题，必须通过四道关键测试：是否便于实现是否能够提供足够的性能是否有合适的操作系统支持是否有大量合适的开发工具（和设计资源）支持其他因素可能会影响这种选择上市时间、企业对特定开发商的偏好或承诺等,How do

5、we choose microprocessor?,PowerBudget,Cost ofGoods,Real-timeConstraints,LegacyCode,Performance,Time toMarket,Landmines,Tool Support,Brute force method of improving performanceBottleneck could be in software design or compiler!Faster isnt always betterPerformance Clock speed Trade-off:As clock speed

6、energy Memory costs increaseOther peripheral devices will cost more,Clock Speed,Evaluating processor performance,Clock speed:but instructions per cycle may differInstructions/sec:but work per instruction may differDhrystone:Synthetic benchmark,developed in 1984SPEC:realistic benchmarks,but oriented

7、to desktopsEEMBC EDN Embedded Benchmark Consortium,www.eembc.orgSuites of benchmarks:automotive,consumer electronics,networking,office automation,telecommunications,von Neumann Architecture,memory,CPU,PC,address,data,IR,ADD r5,r1,r3,200,200,ADD r5,r1,r3,Harvard architecture,CPU,PC,data memory,progra

8、m memory,address,data,address,data,von Neumann vs.Harvard,Harvard cant use self-modifying code.Harvard allows two simultaneous memory fetches.Most DSP use Harvard architecture for streaming data:greater memory bandwidth;more predictable bandwidth.,ARM vs.SHARC,ARM7 is von Neumann architectureWe will

9、 concentrate on ARM7ARM9 is Harvard architectureSHARC is modified Harvard architecture.On chip memory（1Gbit）evenly split between program memory（PM）and data memory（DM）Program memory can be used to store some data.Allows data to be fetched from both memory in parallel,uP Performance,Width of data path

10、 performance（Width of Data Path）2 The most general categorization of processor performanceTypical data bus widths:4,8,16,32,64,128 bits wideWider data busses-greater data processing capabilityData bus width trade-off,the wider data path:Is more complex to designTakes up more room on PC boardsGenerat

11、es greater amounts of energyRequires more costly memory designsIs not compatible with existing hardware,More on data path width,Data path width generally determines functionality4,8 bits-Appliances,modems,simple applications16 bits-Industrial controllers,automotive32 bits-Telecomm,laser printers,hig

12、h-performance apps64 bits-PCs,UNIX workstations,games128,256 bits（VLIW）-Next generationInternal and external data paths may differ in sizeNarrower memory is more economicalMC68000:32-bit internal/16-bit externalMC68008:32-bit internal/8-bit external80C188:16-bit internal/8-bit externalRemember:An 8-

13、bit processor can do almost everything a 64-bit processor can do,it will just take longer to accomplish,Processor Micro-architecture,On-chip instruction/data cache,how big?PipelinesSuperscalar/VLIWTrade-off-high performance costs money,powerAddress bus designAddress bus width:16-36 bits Multiplexed,

14、synchronous,asynchronousProcessor type:CISC,RISC,DSPWhat is the nature of the algorithm to implement?Control rich:CISCData rich:RISCData transforms and mathematical processing:DSP,More on address bus width,The amount of externally accessible memory is defined as the Address Space of the processorCan

15、 vary from 1KB for simple microcontrollers to over 60 GB in high performance processorsSize of the address space doesnt mean that you have that much memory,it only means that the capabilities exist to directly access itProcessors with smaller address spaces can still manipulate larger memory arrays with techniques such as PagingSpecial memory or I/O location used to swap in and out memory pagesExample:An 8-bit Z80 processor w