数字电路与逻辑设计11PPT课件下载推荐.ppt

1、,Digital FundamentalsTenth EditionFloyd,Chapter 11,Summary,Programmable Logic,SPLD:#（Simple PLDs）are the earliest type of array logic used for fixed functions and smaller circuits with a limited number of gates.（The PAL and GAL are both SPLDs）.CPLD:#（Complex PLDs）are multiple SPLDs arrays and inter-

2、connection arrays on a single chip.FPLD:#（Field Programmable Gate Array）are a more flexible arrangement than CPLDs,with much larger capacity.,Programmable Logic Devices（PLDs）are ICs with a large number of gates and flip flops that can be configured with basic software to perform a specific logic fun

3、ction or perform the logic for a complex circuit.Major types of PLDs are:#,Summary,Programmable Logic,Advantages to PLDs include,Reduced complexity of circuit boards Lower power requirements Less board space Simpler testing procedures Higher reliability Design flexibility,Summary,PALs and GALs,PALs

4、have a one time programmable（OTP）array,in which fuses are permanently blown,creating the product terms in an AND array.,All PLDs contain arrays.Two important SPLDs are PALs（Programmable Array Logic）and GALs（Generic Array Logic）.A typical array consists of a matrix of conductors connected in rows and

5、 columns to AND gates.,Simplified AND-OR array,X,A A B B,Summary,X,A A B B,What function is represented by the array?#,Example,Solution,The function represents an XOR gate.,X=AB+AB,PALs are programmed with a specialized programmer that blows selected internal fuse links.After blowing the fuses,the a

6、rray represents the Boolean logic expression for the desired circuit.,PALs and GALs,Summary,The GAL（Generic Array Logic）is similar to a PAL but can be reprogrammed.For this reason,they are useful for new product development（prototyping）and for training purposes.,A A B B,X,GALs were developed by Latt

7、ice Semiconductor.They are high speed,extremely fast devices and can interface with both 3.3 V or 5 V logic signals.,PALs and GALs,Summary,PALs and GALs can be represented with a simplified diagram.A single line can represent multiple gate inputs.The logic shown is for the XOR gate,given previously.

8、,Input buffer,A A B B,Single line with slash indicating multiple AND gate inputs,Fuse blown,Fuse intact,AB,AB,AB+AB,PALs and GALs,Summary,PALs and GALs have large array logic and include output logic that varies in complexity.The output logic is connected to each OR gate and together is referred to

9、as a macrocell.Two types of PAL/GAL macrocells are shown.For these particular macrocells,the I/O pins can serve as an input or an output.,Tristate control,From AND array,From AND array,I/O,I/O,Programmable fuse link to control output polarity,To AND array,To AND array,PALs and GALs,Summary,The PAL16

10、V8 is a typical SPLD.There are 16 pins that can be used as inputs and 8 pins that can be used as outputs.I/O pins are counted as both inputs and outputs.,I1,I2,I3,I4,I5,I6,I7,I8,I9,I/O10,O1,I/O1,I/O2,I/O3,I/O4,I/O5,I/O6,O2,Programmable AND array,PLCC Package,PALs and GALs,Summary,CPLDs,A complex pro

11、grammable logic device（CPLD）has multiple logic array blocks（LABs）that are actually SPLDs on a single IC.LABs are connected via a programmable interconnect array（PIA）.Various CPLDs have different structures for these elements.,The PIA is the interconnection between the LABs.Logic is fitted to the CPL

12、D and routing is determined by a high-level programming language called a hardware description language（HDL）.,Summary,CPLDs,The architecture of a CPLD is the way in which the internal elements are configured.A portion of the Altera MAX 7000 series is shown.This structure is typical for CPLDs althoug

13、h densities,size,speed,and internal factors（macrocells,etc）will vary between manufacturers.,I/O pins,I/O pins,General-purpose inputs,Summary,CPLDs,Macrocells in the Altera MAX 7000 series can generate up to five product terms.For expressions requiring more terms,the output can be expanded as describ

14、ed in the text.,Summary,Macrocells,In addition to combination logic,some macrocells have registered outputs available（using programmable flip-flops）.This allows the CPLD to perform sequential logic.,Summary,FPGAs,A field programmable gate array（FPGA）uses a different architecture than a CPLD.The conf

15、igurable logic block（CLB）is the basic element which is replicated many times.,CLBs are arranged in a row and column structure.Within the CLBs are logic modules joined by local interconnects.Generally,the logic modules are composed of a look-up table（LUT）,a flip-flop,and a MUX that can be used to byp

16、ass the flip-flop for strictly combinational logic.,Summary,FPGAs,Logic modules can be configured for combinational logic,registered logic,or a combination of both.The global interconnects distribute signals（including the clock）to various CLBs.,FPGAs may also have a hard core portion of logic that is put in by the manufacturer and cannot be reprogrammed by the user.These FPGAs are useful in commonly used functions such as I/O interfaces.,Summary,Programmable Logic Software,All manufacturers of progra